107 lines
3.2 KiB
LLVM
107 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=i386-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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define void @t(<4 x float> %A) {
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; SSE-LABEL: t:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0
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; SSE-NEXT: movaps %xmm0, 0
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; SSE-NEXT: retl
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;
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; AVX-LABEL: t:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps {{\.LCPI.*}}, %xmm0, %xmm0
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; AVX-NEXT: vmovaps %xmm0, 0
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; AVX-NEXT: retl
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%tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A
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store <4 x float> %tmp1277, <4 x float>* null
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ret void
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}
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define <4 x float> @t1(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: t1:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: xorps %xmm1, %xmm0
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; SSE-NEXT: retl
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;
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; AVX-LABEL: t1:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retl
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entry:
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%tmp9 = bitcast <4 x float> %a to <4 x i32>
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%tmp10 = bitcast <4 x float> %b to <4 x i32>
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%tmp11 = xor <4 x i32> %tmp9, %tmp10
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%tmp13 = bitcast <4 x i32> %tmp11 to <4 x float>
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ret <4 x float> %tmp13
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}
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define <2 x double> @t2(<2 x double> %a, <2 x double> %b) {
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; SSE-LABEL: t2:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: andps %xmm1, %xmm0
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; SSE-NEXT: retl
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;
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; AVX-LABEL: t2:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retl
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entry:
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%tmp9 = bitcast <2 x double> %a to <2 x i64>
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%tmp10 = bitcast <2 x double> %b to <2 x i64>
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%tmp11 = and <2 x i64> %tmp9, %tmp10
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%tmp13 = bitcast <2 x i64> %tmp11 to <2 x double>
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ret <2 x double> %tmp13
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}
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define void @t3(<4 x float> %a, <4 x float> %b, <4 x float>* %c, <4 x float>* %d) {
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; SSE-LABEL: t3:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; SSE-NEXT: andnps %xmm1, %xmm0
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; SSE-NEXT: orps (%ecx), %xmm0
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; SSE-NEXT: movaps %xmm0, (%eax)
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; SSE-NEXT: retl
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;
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; AVX-LABEL: t3:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
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; AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; AVX-NEXT: vandnps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vorps (%ecx), %xmm0, %xmm0
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; AVX-NEXT: vmovaps %xmm0, (%eax)
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; AVX-NEXT: retl
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entry:
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%tmp3 = load <4 x float>, <4 x float>* %c
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%tmp11 = bitcast <4 x float> %a to <4 x i32>
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%tmp12 = bitcast <4 x float> %b to <4 x i32>
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%tmp13 = xor <4 x i32> %tmp11, < i32 -1, i32 -1, i32 -1, i32 -1 >
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%tmp14 = and <4 x i32> %tmp12, %tmp13
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%tmp27 = bitcast <4 x float> %tmp3 to <4 x i32>
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%tmp28 = or <4 x i32> %tmp14, %tmp27
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%tmp30 = bitcast <4 x i32> %tmp28 to <4 x float>
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store <4 x float> %tmp30, <4 x float>* %d
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ret void
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}
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define <2 x i64> @andn_double_xor(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; SSE-LABEL: andn_double_xor:
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; SSE: # %bb.0:
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; SSE-NEXT: xorps %xmm2, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm0
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; SSE-NEXT: retl
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;
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; AVX-LABEL: andn_double_xor:
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; AVX: # %bb.0:
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; AVX-NEXT: vxorps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vandnps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retl
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%1 = xor <2 x i64> %a, <i64 -1, i64 -1>
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%2 = xor <2 x i64> %b, %c
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%3 = and <2 x i64> %1, %2
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ret <2 x i64> %3
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}
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