323 lines
11 KiB
LLVM
323 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6m-none-eabi < %s | FileCheck %s
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declare i8* @llvm.returnaddress(i32)
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; We don't allocate high registers, so any function not using inline asm will
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; only need to save the low registers.
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define void @low_regs_only() {
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; CHECK-LABEL: low_regs_only:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7}"()
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ret void
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}
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; One high reg clobbered, but no low regs, args or returns. We can use an
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; argument/return register to help save/restore it.
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define void @one_high() {
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; CHECK-LABEL: one_high:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r3, r8
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; CHECK-NEXT: .save {r8}
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; CHECK-NEXT: push {r3}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: bx lr
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entry:
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tail call void asm sideeffect "", "~{r8}"()
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ret void
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}
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; 4 high regs clobbered, but still no low regs, args or returns. We can use all
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; 4 arg/return regs for the save/restore.
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define void @four_high() {
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; CHECK-LABEL: four_high:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mov r3, r11
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; CHECK-NEXT: mov r2, r10
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; CHECK-NEXT: mov r1, r9
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; CHECK-NEXT: mov r0, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r0, r1, r2, r3}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0, r1, r2, r3}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r10, r2
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; CHECK-NEXT: mov r11, r3
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; CHECK-NEXT: bx lr
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entry:
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tail call void asm sideeffect "", "~{r8},~{r9},~{r10},~{r11}"()
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ret void
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}
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; One high and one low register clobbered. lr also gets pushed to simplify the
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; return, and r7 to keep the stack aligned. Here, we could use r0-r3, r4, r7 or
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; lr to save/restore r8.
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define void @one_high_one_low() {
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; CHECK-LABEL: one_high_one_low:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r7, lr}
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; CHECK-NEXT: push {r4, r7, lr}
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; CHECK-NEXT: mov lr, r8
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; CHECK-NEXT: .save {r8}
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; CHECK-NEXT: push {lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: pop {r4, r7, pc}
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entry:
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tail call void asm sideeffect "", "~{r4},~{r8}"()
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ret void
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}
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; All callee-saved registers clobbered, r4-r7 and lr are not live after the
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; first push so can be used for pushing the high registers.
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define void @four_high_four_low() {
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; CHECK-LABEL: four_high_four_low:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: mov lr, r11
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; CHECK-NEXT: mov r7, r10
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; CHECK-NEXT: mov r6, r9
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; CHECK-NEXT: mov r5, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r5, r6, r7, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0, r1, r2, r3}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r10, r2
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; CHECK-NEXT: mov r11, r3
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
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ret void
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}
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; All callee-saved registers clobbered, and frame pointer is requested. r7 now
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; cannot be used while saving/restoring the high regs.
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define void @four_high_four_low_frame_ptr() "frame-pointer"="all" {
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; CHECK-LABEL: four_high_four_low_frame_ptr:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #12
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; CHECK-NEXT: add r7, sp, #12
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; CHECK-NEXT: mov lr, r11
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; CHECK-NEXT: mov r6, r10
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; CHECK-NEXT: mov r5, r9
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; CHECK-NEXT: mov r4, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0, r1, r2, r3}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r10, r2
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; CHECK-NEXT: mov r11, r3
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"()
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ret void
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}
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; All callee-saved registers clobbered, frame pointer is requested and
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; llvm.returnaddress used. r7 and lr now cannot be used while saving/restoring
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; the high regs.
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define void @four_high_four_low_frame_ptr_ret_addr() "frame-pointer"="all" {
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; CHECK-LABEL: four_high_four_low_frame_ptr_ret_addr:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #12
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; CHECK-NEXT: add r7, sp, #12
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; CHECK-NEXT: mov r6, r11
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; CHECK-NEXT: mov r5, r10
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; CHECK-NEXT: mov r4, r9
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; CHECK-NEXT: mov r3, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r3, r4, r5, r6}
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; CHECK-NEXT: mov r0, lr
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0, r1, r2, r3}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r10, r2
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; CHECK-NEXT: mov r11, r3
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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%a = tail call i8* @llvm.returnaddress(i32 0)
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tail call void asm sideeffect "", "r,~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"(i8* %a)
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ret void
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}
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; 4 high regs clobbered, all 4 argument registers used. We push an extra 4 low
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; registers, so that we can use them for saving the high regs.
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define void @four_high_four_arg(i32 %a, i32 %b, i32 %c, i32 %d) {
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; CHECK-LABEL: four_high_four_arg:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r5, r6, r7, lr}
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; CHECK-NEXT: push {r5, r6, r7, lr}
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; CHECK-NEXT: mov lr, r11
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; CHECK-NEXT: mov r7, r10
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; CHECK-NEXT: mov r6, r9
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; CHECK-NEXT: mov r5, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r5, r6, r7, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: pop {r0, r1, r2, r3}
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; CHECK-NEXT: mov r8, r0
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; CHECK-NEXT: mov r9, r1
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; CHECK-NEXT: mov r10, r2
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; CHECK-NEXT: mov r11, r3
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; CHECK-NEXT: pop {r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "r,r,r,r,~{r8},~{r9},~{r10},~{r11}"(i32 %a, i32 %b, i32 %c, i32 %d)
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ret void
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}
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; 4 high regs clobbered, all 4 return registers used. We push an extra 4 low
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; registers, so that we can use them for restoring the high regs.
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define <4 x i32> @four_high_four_return() {
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; CHECK-LABEL: four_high_four_return:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: mov lr, r11
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; CHECK-NEXT: mov r7, r10
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; CHECK-NEXT: mov r6, r9
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; CHECK-NEXT: mov r5, r8
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; CHECK-NEXT: .save {r8, r9, r10, r11}
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; CHECK-NEXT: push {r5, r6, r7, lr}
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r1, #2
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: pop {r4, r5, r6, r7}
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; CHECK-NEXT: mov r8, r4
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; CHECK-NEXT: mov r9, r5
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; CHECK-NEXT: mov r10, r6
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; CHECK-NEXT: mov r11, r7
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "~{r8},~{r9},~{r10},~{r11}"()
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%vecinit = insertelement <4 x i32> undef, i32 1, i32 0
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%vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
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%vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
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%vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
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ret <4 x i32> %vecinit13
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}
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; 4 high regs clobbered, all args & returns used, frame pointer requested and
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; llvm.returnaddress called. This leaves us with 3 low registers available (r4,
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; r5, r6), with which to save 4 high registers, so we have to use two pushes
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; and pops.
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define <4 x i32> @all_of_the_above(i32 %a, i32 %b, i32 %c, i32 %d) "frame-pointer"="all" {
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; CHECK-LABEL: all_of_the_above:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #12
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; CHECK-NEXT: add r7, sp, #12
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; CHECK-NEXT: mov r6, r11
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; CHECK-NEXT: mov r5, r10
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; CHECK-NEXT: mov r4, r9
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; CHECK-NEXT: .save {r9, r10, r11}
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; CHECK-NEXT: push {r4, r5, r6}
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; CHECK-NEXT: mov r6, r8
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; CHECK-NEXT: .save {r8}
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; CHECK-NEXT: push {r6}
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; CHECK-NEXT: .pad #4
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; CHECK-NEXT: sub sp, #4
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; CHECK-NEXT: mov r4, lr
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; CHECK-NEXT: str r4, [sp] @ 4-byte Spill
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: movs r1, #2
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop {r4, r5, r6}
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; CHECK-NEXT: mov r8, r4
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; CHECK-NEXT: mov r9, r5
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; CHECK-NEXT: mov r10, r6
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; CHECK-NEXT: pop {r4}
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; CHECK-NEXT: mov r11, r4
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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entry:
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tail call void asm sideeffect "", "r,r,r,r,~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"(i32 %a, i32 %b, i32 %c, i32 %d)
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%e = tail call i8* @llvm.returnaddress(i32 0)
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%f = ptrtoint i8* %e to i32
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%vecinit = insertelement <4 x i32> undef, i32 %f, i32 0
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%vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
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%vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
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%vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
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ret <4 x i32> %vecinit13
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}
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; When a base pointer is being used, we can safely use it for saving/restoring
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; the high regs because it is set after the last push, and not used at all in the
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; epliogue. We can also use r4 for restoring the registers despite it also being
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; used when restoring sp from fp, as that happens before the first pop.
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define <4 x i32> @base_pointer(i32 %a) {
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; CHECK-LABEL: base_pointer:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r6, r7, lr}
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; CHECK-NEXT: push {r4, r6, r7, lr}
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; CHECK-NEXT: .setfp r7, sp, #8
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; CHECK-NEXT: add r7, sp, #8
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; CHECK-NEXT: mov lr, r9
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; CHECK-NEXT: mov r6, r8
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; CHECK-NEXT: .save {r8, r9}
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; CHECK-NEXT: push {r6, lr}
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; CHECK-NEXT: mov r6, sp
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; CHECK-NEXT: lsls r0, r0, #2
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; CHECK-NEXT: adds r0, r0, #7
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; CHECK-NEXT: movs r1, #7
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; CHECK-NEXT: bics r0, r1
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; CHECK-NEXT: mov r1, sp
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; CHECK-NEXT: subs r0, r1, r0
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; CHECK-NEXT: mov sp, r0
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; CHECK-NEXT: @APP
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; CHECK-NEXT: @NO_APP
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: movs r1, #2
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: movs r3, #4
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; CHECK-NEXT: subs r4, r7, #7
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; CHECK-NEXT: subs r4, #9
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; CHECK-NEXT: mov sp, r4
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; CHECK-NEXT: pop {r4, r6}
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; CHECK-NEXT: mov r8, r4
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; CHECK-NEXT: mov r9, r6
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; CHECK-NEXT: pop {r4, r6, r7, pc}
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entry:
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%b = alloca i32, i32 %a
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call void asm sideeffect "", "r,~{r8},~{r9}"(i32* %b)
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%vecinit = insertelement <4 x i32> undef, i32 1, i32 0
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%vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
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%vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
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%vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
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ret <4 x i32> %vecinit13
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}
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