95 lines
3.5 KiB
LLVM
95 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv1i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv2i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv4i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv8i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv16i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv32i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2)
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ret void
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}
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declare void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32);
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define void @intrinsic_vse1_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind {
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; CHECK-LABEL: intrinsic_vse1_v_nxv64i1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, a1, e8,m8,ta,mu
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; CHECK-NEXT: vse1.v v0, (a0)
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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call void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2)
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ret void
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}
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