1448 lines
42 KiB
LLVM
1448 lines
42 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
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; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: < %s | FileCheck %s -check-prefix=CHECK-BE
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; Vector extract DWord and convert to quad precision.
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@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
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@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
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; Function Attrs: norecurse nounwind
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define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
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; CHECK-LABEL: sdwVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltd v2, v2, 1
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: sdwVecConv2qp:
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; CHECK-BE: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %b, i32 0
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%conv = sitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @sdwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
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; CHECK-LABEL: sdwVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: sdwVecConv2qp1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxspltd v2, v2, 1
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %b, i32 1
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%conv = sitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @sdwVecConv2qp_02(fp128* nocapture %a) {
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; CHECK-LABEL: sdwVecConv2qp_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: lxsd v2, 0(r4)
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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entry:
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%0 = load <2 x i64>, <2 x i64>* @sdwVecMem, align 16
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%vecext = extractelement <2 x i64> %0, i32 0
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%conv = sitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @sdwVecConv2qp1_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
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; CHECK-LABEL: sdwVecConv2qp1_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxsd v2, 8(r4)
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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entry:
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%0 = load <2 x i64>, <2 x i64>* %b, align 16
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%vecext = extractelement <2 x i64> %0, i32 1
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%conv = sitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @udwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {
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; CHECK-LABEL: udwVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxspltd v2, v2, 1
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: udwVecConv2qp:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %b, i32 0
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%conv = uitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @udwVecConv2qp1(fp128* nocapture %a, <2 x i64> %b) {
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; CHECK-LABEL: udwVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: udwVecConv2qp1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxspltd v2, v2, 1
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <2 x i64> %b, i32 1
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%conv = uitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @udwVecConv2qp1_02(fp128* nocapture %a) {
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; CHECK-LABEL: udwVecConv2qp1_02:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC1@toc@ha
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; CHECK-NEXT: ld r4, .LC1@toc@l(r4)
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; CHECK-NEXT: lxsd v2, 8(r4)
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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entry:
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%0 = load <2 x i64>, <2 x i64>* @udwVecMem, align 16
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%vecext = extractelement <2 x i64> %0, i32 1
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%conv = uitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @udwVecConv2qp_03(fp128* nocapture %a, <2 x i64>* nocapture readonly %b) {
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; CHECK-LABEL: udwVecConv2qp_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxsd v2, 0(r4)
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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entry:
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%0 = load <2 x i64>, <2 x i64>* %b, align 16
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%vecext = extractelement <2 x i64> %0, i32 0
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%conv = uitofp i64 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Vector extract Word and convert to quad precision.
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw v2, v2, 3
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; CHECK-NEXT: vextsw2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp:
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; CHECK-BE: vspltw v2, v2, 0
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; CHECK-BE-NEXT: vextsw2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 0
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw v2, v2, 2
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; CHECK-NEXT: vextsw2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp1:
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; CHECK-BE: vextsw2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 1
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextsw2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp2:
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; CHECK-BE: vspltw v2, v2, 2
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; CHECK-BE-NEXT: vextsw2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 2
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw v2, v2, 0
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; CHECK-NEXT: vextsw2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp3:
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; CHECK-BE: vspltw v2, v2, 3
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; CHECK-BE-NEXT: vextsw2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 3
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw v2, v2, 12
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp:
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; CHECK-BE: xxextractuw v2, v2, 0
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 0
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw v2, v2, 8
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp1:
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; CHECK-BE: xxextractuw v2, v2, 4
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 1
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw v2, v2, 4
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp2:
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; CHECK-BE: xxextractuw v2, v2, 8
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 2
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw v2, v2, 0
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; CHECK-NEXT: xscvudqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp3:
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; CHECK-BE: xxextractuw v2, v2, 12
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; CHECK-BE-NEXT: xscvudqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 3
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Vector extract HWord and convert to quad precision.
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; Function Attrs: norecurse nounwind
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define void @shwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) {
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; CHECK-LABEL: shwVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractuh v2, v2, 14
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; CHECK-NEXT: vextsh2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: shwVecConv2qp:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextractuh v2, v2, 0
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; CHECK-BE-NEXT: vextsh2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %b, i32 0
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%conv = sitofp i16 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @shwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) {
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; CHECK-LABEL: shwVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextractuh v2, v2, 12
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; CHECK-NEXT: vextsh2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: shwVecConv2qp1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextractuh v2, v2, 2
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; CHECK-BE-NEXT: vextsh2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <8 x i16> %b, i32 1
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%conv = sitofp i16 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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|
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; Function Attrs: norecurse nounwind
|
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define void @shwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) {
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|
; CHECK-LABEL: shwVecConv2qp2:
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|
; CHECK: # %bb.0: # %entry
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|
; CHECK-NEXT: vextractuh v2, v2, 10
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; CHECK-NEXT: vextsh2d v2, v2
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; CHECK-NEXT: xscvsdqp v2, v2
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; CHECK-NEXT: stxv v2, 0(r3)
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; CHECK-NEXT: blr
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;
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|
; CHECK-BE-LABEL: shwVecConv2qp2:
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|
; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextractuh v2, v2, 4
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; CHECK-BE-NEXT: vextsh2d v2, v2
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; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 2
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @shwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: shwVecConv2qp3:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 8
|
|
; CHECK-NEXT: vextsh2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: shwVecConv2qp3:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 6
|
|
; CHECK-BE-NEXT: vextsh2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 3
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @shwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: shwVecConv2qp4:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 6
|
|
; CHECK-NEXT: vextsh2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: shwVecConv2qp4:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 8
|
|
; CHECK-BE-NEXT: vextsh2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 4
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @shwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: shwVecConv2qp5:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 4
|
|
; CHECK-NEXT: vextsh2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: shwVecConv2qp5:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 10
|
|
; CHECK-BE-NEXT: vextsh2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 5
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @shwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: shwVecConv2qp6:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 2
|
|
; CHECK-NEXT: vextsh2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: shwVecConv2qp6:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 12
|
|
; CHECK-BE-NEXT: vextsh2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 6
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @shwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: shwVecConv2qp7:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 0
|
|
; CHECK-NEXT: vextsh2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: shwVecConv2qp7:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 14
|
|
; CHECK-BE-NEXT: vextsh2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 7
|
|
%conv = sitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 14
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 0
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 0
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp1(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 12
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp1:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 2
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 1
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp2(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 10
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp2:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 4
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 2
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp3(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp3:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 8
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp3:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 6
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 3
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp4(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp4:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 6
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp4:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 8
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 4
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp5(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp5:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 4
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp5:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 10
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 5
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp6(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp6:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 2
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp6:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 12
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 6
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @uhwVecConv2qp7(fp128* nocapture %a, <8 x i16> %b) {
|
|
; CHECK-LABEL: uhwVecConv2qp7:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractuh v2, v2, 0
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: uhwVecConv2qp7:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractuh v2, v2, 14
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <8 x i16> %b, i32 7
|
|
%conv = uitofp i16 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Vector extract Byte and convert to quad precision.
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 15
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 0
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 0
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 14
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp1:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 1
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 1
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 13
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp2:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 2
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 2
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp3:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 12
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp3:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 3
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 3
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp4:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 11
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp4:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 4
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 4
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp5:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 10
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp5:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 5
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 5
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp6:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 9
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp6:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 6
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 6
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp7:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 8
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp7:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 7
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 7
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 7
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp8:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 8
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 8
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp9:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 6
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp9:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 9
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 9
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp10:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 5
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp10:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 10
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 10
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp11:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 4
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp11:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 11
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 11
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp12:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 3
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp12:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 12
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 12
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp13:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 2
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp13:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 13
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 13
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp14:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 1
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp14:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 14
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 14
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @sbVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: sbVecConv2qp15:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 0
|
|
; CHECK-NEXT: vextsb2d v2, v2
|
|
; CHECK-NEXT: xscvsdqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: sbVecConv2qp15:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 15
|
|
; CHECK-BE-NEXT: vextsb2d v2, v2
|
|
; CHECK-BE-NEXT: xscvsdqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 15
|
|
%conv = sitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 15
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 0
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 0
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp1(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 14
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp1:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 1
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 1
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp2(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 13
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp2:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 2
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 2
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp3(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp3:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 12
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp3:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 3
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 3
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp4(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp4:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 11
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp4:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 4
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 4
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp5(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp5:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 10
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp5:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 5
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 5
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp6(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp6:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 9
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp6:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 6
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 6
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp7(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp7:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 8
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp7:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 7
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 7
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp8(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 7
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp8:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 8
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 8
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp9(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp9:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 6
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp9:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 9
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 9
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp10(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp10:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 5
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp10:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 10
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 10
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp11(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp11:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 4
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp11:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 11
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 11
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp12(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp12:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 3
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp12:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 12
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 12
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp13(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp13:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 2
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp13:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 13
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 13
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp14(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp14:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 1
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp14:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 14
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 14
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|
|
|
|
; Function Attrs: norecurse nounwind
|
|
define void @ubVecConv2qp15(fp128* nocapture %a, <16 x i8> %b) {
|
|
; CHECK-LABEL: ubVecConv2qp15:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vextractub v2, v2, 0
|
|
; CHECK-NEXT: xscvudqp v2, v2
|
|
; CHECK-NEXT: stxv v2, 0(r3)
|
|
; CHECK-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: ubVecConv2qp15:
|
|
; CHECK-BE: # %bb.0: # %entry
|
|
; CHECK-BE-NEXT: vextractub v2, v2, 15
|
|
; CHECK-BE-NEXT: xscvudqp v2, v2
|
|
; CHECK-BE-NEXT: stxv v2, 0(r3)
|
|
; CHECK-BE-NEXT: blr
|
|
entry:
|
|
%vecext = extractelement <16 x i8> %b, i32 15
|
|
%conv = uitofp i8 %vecext to fp128
|
|
store fp128 %conv, fp128* %a, align 16
|
|
ret void
|
|
}
|