14 lines
418 B
LLVM
14 lines
418 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that this doesn't fail to select instructions.
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; CHECK: vsplath
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define <8 x i8> @fred(i16 %a0) #0 {
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%t0 = insertelement <4 x i16> undef, i16 %a0, i32 0
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%t1 = shufflevector <4 x i16> %t0, <4 x i16> undef, <4 x i32> zeroinitializer
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%t2 = bitcast <4 x i16> %t1 to <8 x i8>
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ret <8 x i8> %t2
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}
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attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" }
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