35 lines
1.7 KiB
LLVM
35 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -enable-var-scope %s
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s
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; This compute shader has input args that claim that it has 17 sgprs and 5 vgprs
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; in wave dispatch. Ensure that the sgpr and vgpr counts in COMPUTE_PGM_RSRC1
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; are set to reflect that, even though the registers are not used in the shader.
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; GCN-LABEL: {{^}}_amdgpu_cs_main:
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; GCN: .amdgpu_pal_metadata
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; GCN-NEXT: ---
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; GCN-NEXT: amdpal.pipelines:
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; GCN-NEXT: - .hardware_stages:
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; GCN-NEXT: .cs:
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; GCN-NEXT: .entry_point: _amdgpu_cs_main
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; GCN-NEXT: .scratch_memory_size: 0
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; SI-NEXT: .sgpr_count: 0x11
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; VI-NEXT: .sgpr_count: 0x60
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; GFX9-NEXT: .sgpr_count: 0x11
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; SI-NEXT: .vgpr_count: 0x5
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; VI-NEXT: .vgpr_count: 0x5
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; GFX9-NEXT: .vgpr_count: 0x5
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; GCN-NEXT: .registers:
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; SI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
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; VI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}c1
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; GFX9-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81
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; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): 0
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; GCN-NEXT: ...
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; GCN-NEXT: .end_amdgpu_pal_metadata
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define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg, i32 inreg, <2 x i32> inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <5 x i32>) {
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.entry:
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ret void
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}
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