84 lines
2.2 KiB
LLVM
84 lines
2.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; GCN-LABEL: {{^}}scalar_nand_i32_one_use
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; GCN: s_nand_b32
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define amdgpu_kernel void @scalar_nand_i32_one_use(
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i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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entry:
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%and = and i32 %a, %b
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%r0.val = xor i32 %and, -1
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store i32 %r0.val, i32 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_nand_i32_mul_use
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; GCN-NOT: s_nand_b32
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; GCN: s_and_b32
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; GCN: s_not_b32
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; GCN: s_add_i32
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define amdgpu_kernel void @scalar_nand_i32_mul_use(
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i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
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entry:
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%and = and i32 %a, %b
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%r0.val = xor i32 %and, -1
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%r1.val = add i32 %and, %a
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store i32 %r0.val, i32 addrspace(1)* %r0
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store i32 %r1.val, i32 addrspace(1)* %r1
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ret void
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}
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; GCN-LABEL: {{^}}scalar_nand_i64_one_use
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; GCN: s_nand_b64
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define amdgpu_kernel void @scalar_nand_i64_one_use(
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i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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entry:
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%and = and i64 %a, %b
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%r0.val = xor i64 %and, -1
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store i64 %r0.val, i64 addrspace(1)* %r0
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ret void
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}
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; GCN-LABEL: {{^}}scalar_nand_i64_mul_use
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; GCN-NOT: s_nand_b64
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; GCN: s_and_b64
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; GCN: s_not_b64
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; GCN: s_add_u32
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; GCN: s_addc_u32
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define amdgpu_kernel void @scalar_nand_i64_mul_use(
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i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
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entry:
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%and = and i64 %a, %b
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%r0.val = xor i64 %and, -1
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%r1.val = add i64 %and, %a
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store i64 %r0.val, i64 addrspace(1)* %r0
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store i64 %r1.val, i64 addrspace(1)* %r1
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ret void
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}
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; GCN-LABEL: {{^}}vector_nand_i32_one_use
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; GCN-NOT: s_nand_b32
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; GCN: v_and_b32
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; GCN: v_not_b32
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define i32 @vector_nand_i32_one_use(i32 %a, i32 %b) {
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entry:
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%and = and i32 %a, %b
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%r = xor i32 %and, -1
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ret i32 %r
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}
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; GCN-LABEL: {{^}}vector_nand_i64_one_use
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; GCN-NOT: s_nand_b64
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; GCN: v_and_b32
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; GCN: v_and_b32
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; GCN: v_not_b32
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; GCN: v_not_b32
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define i64 @vector_nand_i64_one_use(i64 %a, i64 %b) {
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entry:
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%and = and i64 %a, %b
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%r = xor i64 %and, -1
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ret i64 %r
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}
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