98 lines
4.8 KiB
LLVM
98 lines
4.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s
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; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s
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; FIXME: The register allocator / scheduler should be able to avoid these hazards.
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; VI-LABEL: {{^}}dpp_test:
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; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
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; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}
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; PREGFX10: s_nop 1
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; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
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; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
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define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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store i32 %tmp0, i32 addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}dpp_wait_states:
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; VI-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}}
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; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
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; PREGFX10: s_nop 1
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; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:
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; PREGFX10: s_nop 1
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; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) {
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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%tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0
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store i32 %tmp1, i32 addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}dpp_first_in_bb:
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; VI: ; %endif
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; PREGFX10-NOOPT: s_waitcnt
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; PREGFX10-NOOPT: v_mov_b32_e32
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; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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; PREGFX10-OPT: s_mov_b32
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; PREGFX10-OPT: s_mov_b32
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; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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; PREGFX10: s_nop 1
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; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) {
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%cmp = fcmp oeq float %cond, 0.0
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br i1 %cmp, label %if, label %else
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if:
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%out_val = load float, float addrspace(1)* %out
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%if_val = fadd float %a, %out_val
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br label %endif
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else:
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%in_val = load float, float addrspace(1)* %in
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%else_val = fadd float %b, %in_val
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br label %endif
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endif:
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%val = phi float [%if_val, %if], [%else_val, %else]
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%val_i32 = bitcast float %val to i32
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %val_i32, i32 1, i32 1, i32 1, i1 1) #0
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%tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0
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%tmp2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp1, i32 1, i32 1, i32 1, i1 1) #0
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%tmp_float = bitcast i32 %tmp2 to float
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store float %tmp_float, float addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}mov_dpp64_test:
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; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @mov_dpp64_test(i64 addrspace(1)* %out, i64 %in1) {
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%tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 0) #0
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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; VI-LABEL: {{^}}mov_dpp64_imm_test:
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; VI-OPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9
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; VI-OPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047
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; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], s[[SOLD_LO]]
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; VI-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], s[[SOLD_HI]]
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; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; VI-NOOPT-COUNT-2: v_mov_b32_dpp v{{[0-9]+}}, v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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define amdgpu_kernel void @mov_dpp64_imm_test(i64 addrspace(1)* %out) {
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%tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #0
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32, i32, i32, i1) #0
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attributes #0 = { nounwind readnone convergent }
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