99 lines
3.8 KiB
YAML
99 lines
3.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: writelane_sss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-LABEL: name: writelane_sss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
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; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY3]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
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...
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---
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name: writelane_ssv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $vgpr0
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; CHECK-LABEL: name: writelane_ssv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $vgpr0
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%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
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...
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---
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name: writelane_vsv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; CHECK-LABEL: name: writelane_vsv
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
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...
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---
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name: writelane_vvv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: writelane_vvv
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
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; CHECK: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[V_READFIRSTLANE_B32_]](s32), [[V_READFIRSTLANE_B32_1]](s32), [[COPY2]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
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...
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---
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name: writelane_svv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1
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; CHECK-LABEL: name: writelane_svv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), [[COPY]](s32), [[V_READFIRSTLANE_B32_]](s32), [[COPY2]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = COPY $vgpr1
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%3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.writelane), %0, %1, %2
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...
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