137 lines
5.5 KiB
LLVM
137 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
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define i32 @v_udot4(i32 %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot4:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_udot4:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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define i32 @v_udot4_clamp(i32 %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot4_clamp:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_udot4_clamp:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 true)
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ret i32 %r
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}
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; FIXME: bitcast should not expand
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define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
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; GFX906-LABEL: v_udot4_cast_v4i8:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: s_mov_b32 s5, 8
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; GFX906-NEXT: s_movk_i32 s4, 0xff
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; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX906-NEXT: v_and_or_b32 v0, v0, s4, v1
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; GFX906-NEXT: v_and_b32_e32 v1, s4, v2
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; GFX906-NEXT: v_and_b32_e32 v2, s4, v3
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; GFX906-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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; GFX906-NEXT: v_lshlrev_b32_e32 v2, 24, v2
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; GFX906-NEXT: v_or3_b32 v0, v0, v1, v2
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; GFX906-NEXT: v_lshlrev_b32_sdwa v1, s5, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX906-NEXT: v_and_b32_e32 v2, s4, v6
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; GFX906-NEXT: v_and_b32_e32 v3, s4, v7
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; GFX906-NEXT: v_and_or_b32 v1, v4, s4, v1
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; GFX906-NEXT: v_lshlrev_b32_e32 v2, 16, v2
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; GFX906-NEXT: v_lshlrev_b32_e32 v3, 24, v3
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; GFX906-NEXT: v_or3_b32 v1, v1, v2, v3
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; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v8
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_udot4_cast_v4i8:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_mov_b32 s4, 8
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; GFX10-NEXT: s_movk_i32 s5, 0xff
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; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1
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; GFX10-NEXT: v_and_b32_e32 v1, s5, v2
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; GFX10-NEXT: v_and_b32_e32 v2, s5, v3
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; GFX10-NEXT: v_lshlrev_b32_sdwa v3, s4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
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; GFX10-NEXT: v_and_b32_e32 v5, s5, v6
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; GFX10-NEXT: v_and_b32_e32 v6, s5, v7
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; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
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; GFX10-NEXT: v_lshlrev_b32_e32 v2, 24, v2
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; GFX10-NEXT: v_and_or_b32 v3, v4, s5, v3
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; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v5
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; GFX10-NEXT: v_lshlrev_b32_e32 v5, 24, v6
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; GFX10-NEXT: v_or3_b32 v7, v0, v1, v2
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; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5
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; GFX10-NEXT: v_dot4_u32_u8 v0, v7, v1, v8
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%a.cast = bitcast <4 x i8> %a to i32
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%b.cast = bitcast <4 x i8> %b to i32
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%r = call i32 @llvm.amdgcn.udot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
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ret i32 %r
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}
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define i32 @v_udot4_fnegf32_a(float %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot4_fnegf32_a:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_udot4_fnegf32_a:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%neg.a = fneg float %a
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%cast.neg.a = bitcast float %neg.a to i32
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%r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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define i32 @v_udot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
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; GFX906-LABEL: v_udot4_fnegv2f16_a:
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; GFX906: ; %bb.0:
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; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX906-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
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; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX906-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: v_udot4_fnegv2f16_a:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
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; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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%neg.a = fneg <2 x half> %a
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%cast.neg.a = bitcast <2 x half> %neg.a to i32
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%r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
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ret i32 %r
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}
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declare i32 @llvm.amdgcn.udot4(i32, i32, i32, i1 immarg) #0
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attributes #0 = { nounwind readnone speculatable }
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