llvm-for-llvmta/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
---
name: ffloor_s64_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ffloor_s64_vv
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: %1:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FFLOOR %0
$vgpr0_vgpr1 = COPY %1
...
# FIXME: Constant bus restriction
# ---
# name: ffloor_s64_vs
# legalized: true
# regBankSelected: true
# tracksRegLiveness: true
# body: |
# bb.0:
# liveins: $sgpr0_sgpr1
# %0:sgpr(s64) = COPY $sgpr0_sgpr1
# %1:vgpr(s64) = G_FFLOOR %0
# $vgpr0_vgpr1 = COPY %1
# ...
---
name: ffloor_fneg_s64_vv
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ffloor_fneg_s64_vv
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: %2:vreg_64 = nofpexcept V_FLOOR_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: $vgpr0_vgpr1 = COPY %2
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FNEG %0
%2:vgpr(s64) = G_FFLOOR %1
$vgpr0_vgpr1 = COPY %2
...