166 lines
4.8 KiB
YAML
166 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_const_const
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK: $sgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = G_CONSTANT i32 15
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%1:_(s32) = G_CONSTANT i32 255
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%2:_(s32) = G_AND %0(s32), %1(s32)
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$sgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_const_const_2
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const_2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK: $sgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = G_CONSTANT i32 255
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%1:_(s32) = G_CONSTANT i32 15
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%2:_(s32) = G_AND %0(s32), %1(s32)
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$sgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_const_const_3
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_const_const_3
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766
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; CHECK: $vgpr0 = COPY [[C]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = G_CONSTANT i32 2863311530
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%1:_(s32) = G_CONSTANT i32 4008636142
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%2:_(s32) = G_AND %0(s32), %1(s32)
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$vgpr0 = COPY %2(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_and_and
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_and_and
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
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; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
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; CHECK: $vgpr0 = COPY [[AND]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 15
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%2:_(s32) = G_CONSTANT i32 255
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%3:_(s32) = G_AND %0, %1(s32)
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%4:_(s32) = G_AND %3, %2
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$vgpr0 = COPY %4(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_shl_and
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: test_shl_and
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; CHECK: $sgpr0 = COPY [[SHL]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 4294967264
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%3:_(s32) = G_SHL %0, %1(s32)
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%4:_(s32) = G_AND %3, %2
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$sgpr0 = COPY %4(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_lshr_and
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_lshr_and
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK: $vgpr0 = COPY [[LSHR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $vgpr0
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 5
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%2:_(s32) = G_CONSTANT i32 134217727
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%3:_(s32) = G_LSHR %0, %1(s32)
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%4:_(s32) = G_AND %3, %2
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$vgpr0 = COPY %4(s32)
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SI_RETURN_TO_EPILOG implicit $vgpr0
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...
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---
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name: test_and_non_const
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: test_and_non_const
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK: $sgpr0 = COPY [[LSHR]](s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_CONSTANT i32 16
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%3:_(s32) = G_CONSTANT i32 65535
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%4:_(s32) = G_OR %1, %3
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%5:_(s32) = G_LSHR %0, %2(s32)
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%6:_(s32) = G_AND %5, %4
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$sgpr0 = COPY %6(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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---
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name: test_sext_inreg
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_sext_inreg
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; CHECK: %cst_1:_(s32) = G_CONSTANT i32 -5
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; CHECK: $sgpr0 = COPY %cst_1(s32)
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; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
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%cst_1:_(s32) = G_CONSTANT i32 -5
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; 000 ... 1011
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%cst_11:_(s32) = G_CONSTANT i32 11
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; Sext from the 4th bit -> 111 ... 1011 = -5
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%sext_inreg_11:_(s32) = G_SEXT_INREG %cst_11, 4
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%and:_(s32) = G_AND %cst_1(s32), %sext_inreg_11(s32)
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$sgpr0 = COPY %and(s32)
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SI_RETURN_TO_EPILOG implicit $sgpr0
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...
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