80 lines
3.5 KiB
LLVM
80 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
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; Test that redundant ptest instruction is removed when using a flag setting brk
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define i32 @brkpb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkpb:
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; CHECK: brkpbs p0.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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define i32 @brkb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brkb:
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; CHECK: brkbs p0.b, p0/z, p1.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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define i32 @brkn(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkn:
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; CHECK: brkns p2.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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; Test that ptest instruction is not removed when using a non-flag setting brk
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define i32 @brkpb_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkpb_neg:
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; CHECK: brkpb p0.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: ptest p1, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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define i32 @brkb_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
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; CHECK-LABEL: brkb_neg:
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; CHECK: brkb p0.b, p0/z, p1.b
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; CHECK-NEXT: ptest p1, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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define i32 @brkn_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: brkn_neg:
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; CHECK: brkn p2.b, p0/z, p1.b, p2.b
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; CHECK-NEXT: ptest p1, p2.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
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%2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
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%conv = zext i1 %2 to i32
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ret i32 %conv
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
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declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
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