139 lines
5.5 KiB
LLVM
139 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s --check-prefixes=CHECK
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s < %t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; Should codegen to a nop, since idx is zero.
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define <2 x i64> @extract_v2i64_nxv2i64(<vscale x 2 x i64> %vec) nounwind {
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; CHECK-LABEL: extract_v2i64_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 0)
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ret <2 x i64> %retval
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}
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; Goes through memory currently; idx != 0.
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define <2 x i64> @extract_v2i64_nxv2i64_idx1(<vscale x 2 x i64> %vec) nounwind {
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; CHECK-LABEL: extract_v2i64_nxv2i64_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1d { z0.d }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #3
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64> %vec, i64 1)
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ret <2 x i64> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <4 x i32> @extract_v4i32_nxv4i32(<vscale x 4 x i32> %vec) nounwind {
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; CHECK-LABEL: extract_v4i32_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 0)
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ret <4 x i32> %retval
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}
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; Goes through memory currently; idx != 0.
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define <4 x i32> @extract_v4i32_nxv4i32_idx1(<vscale x 4 x i32> %vec) nounwind {
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; CHECK-LABEL: extract_v4i32_nxv4i32_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cntw x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1w { z0.s }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #2
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32> %vec, i64 1)
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ret <4 x i32> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <8 x i16> @extract_v8i16_nxv8i16(<vscale x 8 x i16> %vec) nounwind {
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; CHECK-LABEL: extract_v8i16_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 0)
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ret <8 x i16> %retval
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}
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; Goes through memory currently; idx != 0.
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define <8 x i16> @extract_v8i16_nxv8i16_idx1(<vscale x 8 x i16> %vec) nounwind {
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; CHECK-LABEL: extract_v8i16_nxv8i16_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: cnth x8
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: st1h { z0.h }, p0, [sp]
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; CHECK-NEXT: lsl x8, x8, #1
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16> %vec, i64 1)
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ret <8 x i16> %retval
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}
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; Should codegen to a nop, since idx is zero.
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define <16 x i8> @extract_v16i8_nxv16i8(<vscale x 16 x i8> %vec) nounwind {
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; CHECK-LABEL: extract_v16i8_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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; CHECK-NEXT: ret
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%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 0)
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ret <16 x i8> %retval
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}
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; Goes through memory currently; idx != 0.
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define <16 x i8> @extract_v16i8_nxv16i8_idx1(<vscale x 16 x i8> %vec) nounwind {
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; CHECK-LABEL: extract_v16i8_nxv16i8_idx1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: sub x8, x8, #1 // =1
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmp x8, #1 // =1
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; CHECK-NEXT: st1b { z0.b }, p0, [sp]
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; CHECK-NEXT: csinc x8, x8, xzr, lo
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%retval = call <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8> %vec, i64 1)
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ret <16 x i8> %retval
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}
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declare <2 x i64> @llvm.experimental.vector.extract.v2i64.nxv2i64(<vscale x 2 x i64>, i64)
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declare <4 x i32> @llvm.experimental.vector.extract.v4i32.nxv4i32(<vscale x 4 x i32>, i64)
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declare <8 x i16> @llvm.experimental.vector.extract.v8i16.nxv8i16(<vscale x 8 x i16>, i64)
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declare <16 x i8> @llvm.experimental.vector.extract.v16i8.nxv16i8(<vscale x 16 x i8>, i64)
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