302 lines
12 KiB
LLVM
302 lines
12 KiB
LLVM
; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=cortex-a65ae < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-e1 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n1 < %s | FileCheck %s
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; RUN: llc -mtriple aarch64-none-linux-gnu -mcpu=neoverse-n2 < %s | FileCheck %s
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declare <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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declare <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32>, <8 x i8>, <8 x i8>)
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declare <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32>, <16 x i8>, <16 x i8>)
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define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_u32:
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; CHECK: udot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdot_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.8b
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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entry:
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; CHECK-LABEL: test_vdotq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.16b
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_u32:
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; CHECK: udot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_u32:
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; CHECK: udot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_lane_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_lane_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdot_laneq_s32:
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; CHECK: sdot v0.2s, v1.8b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
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entry:
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; CHECK-LABEL: test_vdotq_laneq_s32:
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; CHECK: sdot v0.4s, v1.16b, v2.4b[1]
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%.cast = bitcast <16 x i8> %c to <4 x i32>
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%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define fastcc void @test_sdot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
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entry:
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; CHECK-LABEL: test_sdot_v4i8:
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; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%3 = bitcast i8* %0 to i32*
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%4 = load i8, i8* %1, align 1
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%5 = sext i8 %4 to i32
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%6 = load i8, i8* %2, align 1
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%7 = sext i8 %6 to i32
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%8 = mul nsw i32 %7, %5
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%9 = getelementptr inbounds i8, i8* %1, i64 1
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%10 = load i8, i8* %9, align 1
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%11 = sext i8 %10 to i32
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%12 = getelementptr inbounds i8, i8* %2, i64 1
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%13 = load i8, i8* %12, align 1
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%14 = sext i8 %13 to i32
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%15 = mul nsw i32 %14, %11
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%16 = add nsw i32 %15, %8
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%17 = getelementptr inbounds i8, i8* %1, i64 2
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%18 = load i8, i8* %17, align 1
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%19 = sext i8 %18 to i32
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%20 = getelementptr inbounds i8, i8* %2, i64 2
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%21 = load i8, i8* %20, align 1
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%22 = sext i8 %21 to i32
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%23 = mul nsw i32 %22, %19
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%24 = add nsw i32 %23, %16
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%25 = getelementptr inbounds i8, i8* %1, i64 3
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%26 = load i8, i8* %25, align 1
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%27 = sext i8 %26 to i32
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%28 = getelementptr inbounds i8, i8* %2, i64 3
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%29 = load i8, i8* %28, align 1
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%30 = sext i8 %29 to i32
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%31 = mul nsw i32 %30, %27
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%32 = add nsw i32 %31, %24
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store i32 %32, i32* %3, align 64
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ret void
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}
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define fastcc void @test_udot_v4i8(i8* noalias nocapture %0, i8* noalias nocapture readonly %1, i8* noalias nocapture readonly %2) {
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entry:
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; CHECK-LABEL: test_udot_v4i8:
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; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%3 = bitcast i8* %0 to i32*
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%4 = load i8, i8* %1, align 1
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%5 = zext i8 %4 to i32
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%6 = load i8, i8* %2, align 1
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%7 = zext i8 %6 to i32
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%8 = mul nsw i32 %7, %5
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%9 = getelementptr inbounds i8, i8* %1, i64 1
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%10 = load i8, i8* %9, align 1
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%11 = zext i8 %10 to i32
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%12 = getelementptr inbounds i8, i8* %2, i64 1
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%13 = load i8, i8* %12, align 1
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%14 = zext i8 %13 to i32
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%15 = mul nsw i32 %14, %11
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%16 = add nsw i32 %15, %8
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%17 = getelementptr inbounds i8, i8* %1, i64 2
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%18 = load i8, i8* %17, align 1
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%19 = zext i8 %18 to i32
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%20 = getelementptr inbounds i8, i8* %2, i64 2
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%21 = load i8, i8* %20, align 1
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%22 = zext i8 %21 to i32
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%23 = mul nsw i32 %22, %19
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%24 = add nsw i32 %23, %16
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%25 = getelementptr inbounds i8, i8* %1, i64 3
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%26 = load i8, i8* %25, align 1
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%27 = zext i8 %26 to i32
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%28 = getelementptr inbounds i8, i8* %2, i64 3
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%29 = load i8, i8* %28, align 1
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%30 = zext i8 %29 to i32
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%31 = mul nsw i32 %30, %27
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%32 = add nsw i32 %31, %24
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store i32 %32, i32* %3, align 64
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ret void
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}
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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define i32 @test_udot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test_udot_v8i8:
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; CHECK: udot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%0 = bitcast i8* %a to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0
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%2 = zext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %b to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3
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%5 = zext <8 x i8> %4 to <8 x i32>
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%6 = mul nuw nsw <8 x i32> %5, %2
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%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
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ret i32 %7
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}
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define i32 @test_sdot_v8i8(i8* nocapture readonly %a, i8* nocapture readonly %b) {
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entry:
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; CHECK-LABEL: test_sdot_v8i8:
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; CHECK: sdot {{v[0-9]+}}.2s, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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%0 = bitcast i8* %a to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0
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%2 = sext <8 x i8> %1 to <8 x i32>
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%3 = bitcast i8* %b to <8 x i8>*
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%4 = load <8 x i8>, <8 x i8>* %3
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%5 = sext <8 x i8> %4 to <8 x i32>
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%6 = mul nsw <8 x i32> %5, %2
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%7 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %6)
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ret i32 %7
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}
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declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
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define i32 @test_udot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
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entry:
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; CHECK-LABEL: test_udot_v16i8:
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; CHECK: udot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%0 = bitcast i8* %a to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = zext <16 x i8> %1 to <16 x i32>
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%3 = bitcast i8* %b to <16 x i8>*
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%4 = load <16 x i8>, <16 x i8>* %3
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%5 = zext <16 x i8> %4 to <16 x i32>
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%6 = mul nuw nsw <16 x i32> %5, %2
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%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
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%op.extra = add i32 %7, %sum
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ret i32 %op.extra
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}
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define i32 @test_udot_v16i8_2(i8* nocapture readonly %a1) {
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; CHECK-LABEL: test_udot_v16i8_2:
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; CHECK: movi {{v[0-9]+}}.16b, #1
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; CHECK: movi {{v[0-9]+}}.2d, #0000000000000000
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; CHECK: udot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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; CHECK: addv s0, {{v[0-9]+}}.4s
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entry:
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%0 = bitcast i8* %a1 to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = zext <16 x i8> %1 to <16 x i32>
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%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
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ret i32 %3
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}
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define i32 @test_sdot_v16i8(i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %sum) {
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entry:
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; CHECK-LABEL: test_sdot_v16i8:
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; CHECK: sdot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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%0 = bitcast i8* %a to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = sext <16 x i8> %1 to <16 x i32>
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%3 = bitcast i8* %b to <16 x i8>*
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%4 = load <16 x i8>, <16 x i8>* %3
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%5 = sext <16 x i8> %4 to <16 x i32>
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%6 = mul nsw <16 x i32> %5, %2
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%7 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %6)
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%op.extra = add nsw i32 %7, %sum
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ret i32 %op.extra
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}
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define i32 @test_sdot_v16i8_2(i8* nocapture readonly %a1) {
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; CHECK-LABEL: test_sdot_v16i8_2:
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; CHECK: movi {{v[0-9]+}}.16b, #1
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; CHECK: movi {{v[0-9]+}}.2d, #0000000000000000
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; CHECK: sdot {{v[0-9]+}}.4s, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
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; CHECK: addv s0, {{v[0-9]+}}.4s
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entry:
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%0 = bitcast i8* %a1 to <16 x i8>*
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%1 = load <16 x i8>, <16 x i8>* %0
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%2 = sext <16 x i8> %1 to <16 x i32>
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%3 = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %2)
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ret i32 %3
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}
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