llvm-for-llvmta/test/CodeGen/AArch64/combine-loads.ll

20 lines
664 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -O0 -mtriple=aarch64-unknown-unknown | FileCheck %s
define <2 x i64> @z(i64* nocapture nonnull readonly %p) {
; CHECK-LABEL: z:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: ldr x8, [x0, #8]
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret
%b = load i64, i64* %p
%p2 = getelementptr i64, i64* %p, i64 1
%bb = load i64, i64* %p2
%r1 = insertelement <2 x i64> zeroinitializer, i64 %b, i32 0
%r2 = insertelement <2 x i64> %r1, i64 %bb, i32 1
ret <2 x i64> %r2
}