249 lines
8.4 KiB
C++
249 lines
8.4 KiB
C++
//===-- X86TileConfig.cpp - Tile Register Configure----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Pass to config the shape of AMX physical registers
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/// AMX register need to be configured before use. In X86PreTileConfig pass
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/// the pldtilecfg instruction is inserted, however at that time we don't
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/// know the shape of each physical tile registers, because the register
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/// allocation is not done yet. This pass runs after egister allocation
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/// pass. It collects the shape information of each physical tile register
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/// and store the shape in the stack slot that is allocated for load config
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/// to tile config register.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TileShapeInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "tile-config"
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namespace {
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class X86TileConfig : public MachineFunctionPass {
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// context
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MachineFunction *MF = nullptr;
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const X86Subtarget *ST = nullptr;
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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MachineDominatorTree *DomTree = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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VirtRegMap *VRM = nullptr;
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LiveIntervals *LIS = nullptr;
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MachineInstr *getTileConfigPoint();
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void tileConfig();
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public:
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X86TileConfig() : MachineFunctionPass(ID) {}
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/// Return the pass name.
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StringRef getPassName() const override { return "Tile Register Configure"; }
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/// X86TileConfig analysis usage.
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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/// Perform register allocation.
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bool runOnMachineFunction(MachineFunction &mf) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoPHIs);
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}
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static char ID;
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};
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} // end anonymous namespace
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char X86TileConfig::ID = 0;
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INITIALIZE_PASS_BEGIN(X86TileConfig, "tileconfig", "Tile Register Configure",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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INITIALIZE_PASS_END(X86TileConfig, "tileconfig", "Tile Register Configure",
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false, false)
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void X86TileConfig::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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AU.addRequired<VirtRegMap>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static unsigned getTilePhysRegIndex(Register PhysReg) {
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assert((PhysReg >= X86::TMM0 && X86::TMM0 <= X86::TMM7) &&
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"Tile register number is invalid");
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return (PhysReg - X86::TMM0);
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}
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static MachineInstr *
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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Register SrcReg, unsigned BitSize, int FrameIdx, int Offset,
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const TargetInstrInfo *TII, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) {
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unsigned SubIdx = (BitSize == 8) ? X86::sub_8bit : X86::sub_16bit;
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unsigned Opc = (BitSize == 8) ? X86::MOV8mr : X86::MOV16mr;
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if (BitSize == TRI->getRegSizeInBits(*RC))
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SubIdx = 0;
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MachineInstr *NewMI =
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addFrameReference(BuildMI(MBB, MI, DebugLoc(), TII->get(Opc)), FrameIdx,
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Offset)
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.addReg(SrcReg, 0, SubIdx);
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return NewMI;
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}
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static MachineInstr *storeImmToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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int64_t Imm, unsigned BitSize,
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int FrameIdx, int Offset,
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const TargetInstrInfo *TII) {
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unsigned Opc = (BitSize == 8) ? X86::MOV8mi : X86::MOV16mi;
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return addFrameReference(BuildMI(MBB, MI, DebugLoc(), TII->get(Opc)),
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FrameIdx, Offset)
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.addImm(Imm);
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}
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MachineInstr *X86TileConfig::getTileConfigPoint() {
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for (MachineBasicBlock &MBB : *MF) {
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// Traverse the basic block.
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for (MachineInstr &MI : MBB)
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// Refer X86PreTileConfig.cpp.
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// We only support one tile config for now.
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if (MI.getOpcode() == X86::PLDTILECFG)
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return &MI;
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}
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return nullptr;
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}
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void X86TileConfig::tileConfig() {
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MachineInstr *MI = getTileConfigPoint();
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if (!MI)
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return;
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MachineBasicBlock *MBB = MI->getParent();
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int SS = MI->getOperand(1).getIndex();
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BitVector PhysRegs(TRI->getNumRegs());
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// Fill in the palette first.
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auto *NewMI = storeImmToStackSlot(*MBB, *MI, 1, 8, SS, 0, TII);
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LIS->InsertMachineInstrInMaps(*NewMI);
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// Fill in the shape of each tile physical register.
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for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
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Register VirtReg = Register::index2VirtReg(i);
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if (MRI->reg_nodbg_empty(VirtReg))
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continue;
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const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
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if (RC.getID() != X86::TILERegClassID)
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continue;
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Register PhysReg = VRM->getPhys(VirtReg);
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if (PhysRegs.test(PhysReg))
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continue;
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PhysRegs.set(PhysReg);
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ShapeT Shape = VRM->getShape(VirtReg);
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Register RowReg = Shape.getRow()->getReg();
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Register ColReg = Shape.getCol()->getReg();
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// Here is the data format for the tile config.
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// 0 palette
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// 1 start_row
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// 2-15 reserved, must be zero
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// 16-17 tile0.colsb Tile 0 bytes per row.
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// 18-19 tile1.colsb Tile 1 bytes per row.
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// 20-21 tile2.colsb Tile 2 bytes per row.
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// ... (sequence continues)
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// 30-31 tile7.colsb Tile 7 bytes per row.
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// 32-47 reserved, must be zero
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// 48 tile0.rows Tile 0 rows.
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// 49 tile1.rows Tile 1 rows.
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// 50 tile2.rows Tile 2 rows.
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// ... (sequence continues)
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// 55 tile7.rows Tile 7 rows.
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// 56-63 reserved, must be zero
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unsigned Index = getTilePhysRegIndex(PhysReg);
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int RowOffset = 48 + Index;
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int ColOffset = 16 + Index * 2;
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unsigned BitSize = 8;
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for (const auto &Pair : {std::make_pair(RowReg, RowOffset),
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std::make_pair(ColReg, ColOffset)}) {
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int64_t Imm;
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int ImmCount = 0;
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// All def must be the same value, otherwise it is invalid MIs.
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// Immediate is prefered.
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for (const MachineOperand &MO : MRI->def_operands(Pair.first)) {
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const auto *Inst = MO.getParent();
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if (Inst->isMoveImmediate()) {
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ImmCount++;
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Imm = Inst->getOperand(1).getImm();
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break;
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}
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}
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auto StoreConfig = [&](int Offset) {
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MachineInstr *NewMI = nullptr;
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if (ImmCount)
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NewMI = storeImmToStackSlot(*MBB, *MI, Imm, BitSize, SS, Offset, TII);
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else {
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const TargetRegisterClass *RC = MRI->getRegClass(Pair.first);
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NewMI = storeRegToStackSlot(*MBB, *MI, Pair.first, BitSize, SS,
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Offset, TII, RC, TRI);
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}
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SlotIndex SIdx = LIS->InsertMachineInstrInMaps(*NewMI);
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if (!ImmCount) {
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// Extend the live interval.
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SmallVector<SlotIndex, 8> EndPoints = {SIdx.getRegSlot()};
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LiveInterval &Int = LIS->getInterval(Pair.first);
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LIS->extendToIndices(Int, EndPoints);
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}
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};
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StoreConfig(Pair.second);
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BitSize += 8;
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}
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}
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}
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bool X86TileConfig::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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MRI = &mf.getRegInfo();
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ST = &mf.getSubtarget<X86Subtarget>();
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TRI = ST->getRegisterInfo();
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TII = mf.getSubtarget().getInstrInfo();
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DomTree = &getAnalysis<MachineDominatorTree>();
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VRM = &getAnalysis<VirtRegMap>();
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LIS = &getAnalysis<LiveIntervals>();
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if (VRM->isShapeMapEmpty())
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return false;
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tileConfig();
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return true;
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}
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FunctionPass *llvm::createX86TileConfigPass() { return new X86TileConfig(); }
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