475 lines
23 KiB
TableGen
475 lines
23 KiB
TableGen
//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Intel Silvermont to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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def SLMModel : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and SLM can decode 2
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// instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 32; // Based on the reorder buffer.
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let LoadLatency = 3;
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let MispredictPenalty = 10;
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let PostRAScheduler = 1;
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// For small loops, expand by a small factor to hide the backedge cost.
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let LoopMicroOpBufferSize = 10;
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// FIXME: SSE4 is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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}
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let SchedModel = SLMModel in {
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// Silvermont has 5 reservation stations for micro-ops
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def SLM_IEC_RSV0 : ProcResource<1>;
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def SLM_IEC_RSV1 : ProcResource<1>;
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def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
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def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
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def SLM_MEC_RSV : ProcResource<1>;
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// Many micro-ops are capable of issuing on multiple ports.
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def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;
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def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;
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def SLMDivider : ProcResource<1>;
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def SLMFPMultiplier : ProcResource<1>;
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def SLMFPDivider : ProcResource<1>;
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// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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def : ReadAdvance<ReadAfterVecLd, 3>;
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def : ReadAdvance<ReadAfterVecXLd, 3>;
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def : ReadAdvance<ReadAfterVecYLd, 3>;
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def : ReadAdvance<ReadInt2Fpu, 0>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when queued in the reservation station.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [1], int UOps = 1,
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int LoadLat = 3> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
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// the latency (default = 3).
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def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
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let Latency = !add(Lat, LoadLat);
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let ResourceCycles = !listconcat([1], Res);
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let NumMicroOps = UOps;
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}
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}
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// A folded store needs a cycle on MEC_RSV for the store data, but it does not
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// need an extra port cycle to recompute the address.
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def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
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def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
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def : WriteRes<WriteZero, []>;
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// Load/store MXCSR.
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// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
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def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
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def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; }
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// Treat misc copies as a move.
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def : InstRW<[WriteMove], (instrs COPY)>;
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defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>;
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defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>;
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defm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 3>;
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defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>;
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defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>;
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defm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>;
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defm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>;
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defm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>;
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defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>;
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defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>;
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defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
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defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
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defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>;
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defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>;
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defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>;
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defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move.
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def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
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def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
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// FIXME Latency and NumMicrOps?
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let ResourceCycles = [2,1];
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}
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defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
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defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
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defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
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defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
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// This is for simple LEAs with one or two input operands.
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// The complex ones can only execute on port 1, and they require two cycles on
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// the port to read all inputs. We don't model that.
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def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
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// Bit counts.
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defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>;
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defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>;
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defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>;
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defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>;
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defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>;
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// BMI1 BEXTR/BLS, BMI2 BZHI
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defm : X86WriteResPairUnsupported<WriteBEXTR>;
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defm : X86WriteResPairUnsupported<WriteBLS>;
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defm : X86WriteResPairUnsupported<WriteBZHI>;
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defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
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// Scalar and vector floating point.
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defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>;
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defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>;
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def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFMaskedStore32, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFMaskedStore32Y, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFMaskedStore64, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFMaskedStore64Y, [SLM_MEC_RSV]>;
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def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>;
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def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>;
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def : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>;
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defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>;
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defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>;
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defm : X86WriteResPairUnsupported<WriteFAddZ>;
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defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 4, [2]>;
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defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 4, [2]>;
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defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
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defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>;
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defm : X86WriteResPairUnsupported<WriteFCmpZ>;
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defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>;
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defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
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defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFComX, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
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defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
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defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
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defm : X86WriteResPairUnsupported<WriteFMulZ>;
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defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
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defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>;
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defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>;
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defm : X86WriteResPairUnsupported<WriteFMul64Z>;
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defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>;
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defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
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defm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
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defm : X86WriteResPairUnsupported<WriteFDivZ>;
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defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>;
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defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
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defm : SLMWriteResPair<WriteFDiv64Y, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
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defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
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defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFRcpY, [SLM_FPC_RSV0], 5>;
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defm : X86WriteResPairUnsupported<WriteFRcpZ>;
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defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 5>;
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defm : SLMWriteResPair<WriteFRsqrtY, [SLM_FPC_RSV0], 5>;
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defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
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defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>;
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defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
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defm : SLMWriteResPair<WriteFSqrtY, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
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defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
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defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>;
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defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
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defm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
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defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
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defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>;
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defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteDPPSY, [SLM_FPC_RSV1], 3>;
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defm : X86WriteResPairUnsupported<WriteDPPSZ>;
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defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>;
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defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>;
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defm : X86WriteResPairUnsupported<WriteFRndZ>;
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defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WriteFLogicZ>;
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defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WriteFTestZ>;
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defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
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defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
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defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>;
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// Conversion between integer and float.
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defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
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defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
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defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
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defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
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defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
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defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV01], 4>;
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defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>;
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defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
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// Vector integer operations.
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def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; }
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def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecMaskedStore32, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecMaskedStore32Y, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecMaskedStore64, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecMaskedStore64Y, [SLM_MEC_RSV]>;
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def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>;
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def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>;
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def : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>;
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def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>;
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def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>;
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defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
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defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
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defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
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defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WriteVecTestZ>;
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defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WriteVecALUZ>;
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defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 4>;
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defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
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// FIXME: The below is closer to correct, but caused some perf regressions.
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//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>;
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defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0], 4>;
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defm : X86WriteResPairUnsupported<WritePMULLDZ>;
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defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteShuffleZ>;
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defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
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defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>;
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defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>;
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defm : X86WriteResPairUnsupported<WriteBlendZ>;
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defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>;
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defm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0], 7>;
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defm : X86WriteResPairUnsupported<WriteMPSADZ>;
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defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 4>;
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defm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0], 4>;
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defm : X86WriteResPairUnsupported<WritePSADBWZ>;
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defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>;
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// Vector insert/extract operations.
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defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>;
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def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
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def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
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let Latency = 4;
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let NumMicroOps = 2;
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let ResourceCycles = [1, 2];
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}
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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////////////////////////////////////////////////////////////////////////////////
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defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 6, [6], 4>;
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defm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 6, [6], 4>;
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defm : X86WriteResPairUnsupported<WriteFHAddZ>;
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defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 1>;
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defm : SLMWriteResPair<WritePHAddY, [SLM_FPC_RSV01], 1>;
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defm : X86WriteResPairUnsupported<WritePHAddZ>;
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// String instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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defm : SLMWriteResPair<WritePCmpIStrM, [SLM_FPC_RSV0], 13, [13]>;
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// Packed Compare Explicit Length Strings, Return Mask
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defm : SLMWriteResPair<WritePCmpEStrM, [SLM_FPC_RSV0], 17, [17]>;
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// Packed Compare Implicit Length Strings, Return Index
|
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defm : SLMWriteResPair<WritePCmpIStrI, [SLM_FPC_RSV0], 17, [17]>;
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// Packed Compare Explicit Length Strings, Return Index
|
|
defm : SLMWriteResPair<WritePCmpEStrI, [SLM_FPC_RSV0], 21, [21]>;
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// MOVMSK Instructions.
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def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
|
|
def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
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|
def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; }
|
|
def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
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|
|
|
// AES Instructions.
|
|
defm : SLMWriteResPair<WriteAESDecEnc, [SLM_FPC_RSV0], 8, [5]>;
|
|
defm : SLMWriteResPair<WriteAESIMC, [SLM_FPC_RSV0], 8, [5]>;
|
|
defm : SLMWriteResPair<WriteAESKeyGen, [SLM_FPC_RSV0], 8, [5]>;
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|
|
|
// Carry-less multiplication instructions.
|
|
defm : SLMWriteResPair<WriteCLMul, [SLM_FPC_RSV0], 10, [10]>;
|
|
|
|
def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; }
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|
def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
|
|
def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
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|
def : WriteRes<WriteNop, []>;
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|
|
|
// AVX/FMA is not supported on that architecture, but we should define the basic
|
|
// scheduling resources anyway.
|
|
def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
|
|
defm : X86WriteResPairUnsupported<WriteFBlendY>;
|
|
defm : X86WriteResPairUnsupported<WriteFBlendZ>;
|
|
defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendY>;
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
|
|
defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 3>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
|
|
defm : X86WriteResPairUnsupported<WriteFShuffle256>;
|
|
defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
|
|
defm : X86WriteResPairUnsupported<WriteShuffle256>;
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
|
|
defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>;
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
|
|
defm : X86WriteResPairUnsupported<WriteFMA>;
|
|
defm : X86WriteResPairUnsupported<WriteFMAX>;
|
|
defm : X86WriteResPairUnsupported<WriteFMAY>;
|
|
defm : X86WriteResPairUnsupported<WriteFMAZ>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
|
|
defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PH>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
|
|
|
|
// Remaining SLM instrs.
|
|
|
|
def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
|
|
let Latency = 4;
|
|
let NumMicroOps = 2;
|
|
let ResourceCycles = [4];
|
|
}
|
|
def: InstRW<[SLMWriteResGroup1rr], (instrs PADDQrr, PSUBQrr, PCMPEQQrr)>;
|
|
|
|
def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
|
|
let Latency = 7;
|
|
let NumMicroOps = 3;
|
|
let ResourceCycles = [1,4];
|
|
}
|
|
def: InstRW<[SLMWriteResGroup1rm], (instrs PADDQrm, PSUBQrm, PCMPEQQrm)>;
|
|
|
|
} // SchedModel
|