360 lines
11 KiB
C++
360 lines
11 KiB
C++
//===-- VEISelDAGToDAG.cpp - A dag to dag inst selector for VE ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the VE target.
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//
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//===----------------------------------------------------------------------===//
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#include "VETargetMachine.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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/// Convert a DAG integer condition code to a VE ICC condition.
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inline static VECC::CondCode intCondCode2Icc(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unknown integer condition code!");
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case ISD::SETEQ:
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return VECC::CC_IEQ;
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case ISD::SETNE:
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return VECC::CC_INE;
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case ISD::SETLT:
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return VECC::CC_IL;
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case ISD::SETGT:
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return VECC::CC_IG;
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case ISD::SETLE:
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return VECC::CC_ILE;
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case ISD::SETGE:
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return VECC::CC_IGE;
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case ISD::SETULT:
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return VECC::CC_IL;
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case ISD::SETULE:
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return VECC::CC_ILE;
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case ISD::SETUGT:
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return VECC::CC_IG;
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case ISD::SETUGE:
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return VECC::CC_IGE;
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}
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}
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/// Convert a DAG floating point condition code to a VE FCC condition.
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inline static VECC::CondCode fpCondCode2Fcc(ISD::CondCode CC) {
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switch (CC) {
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default:
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llvm_unreachable("Unknown fp condition code!");
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case ISD::SETFALSE:
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return VECC::CC_AF;
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case ISD::SETEQ:
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case ISD::SETOEQ:
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return VECC::CC_EQ;
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case ISD::SETNE:
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case ISD::SETONE:
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return VECC::CC_NE;
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case ISD::SETLT:
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case ISD::SETOLT:
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return VECC::CC_L;
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case ISD::SETGT:
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case ISD::SETOGT:
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return VECC::CC_G;
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case ISD::SETLE:
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case ISD::SETOLE:
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return VECC::CC_LE;
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case ISD::SETGE:
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case ISD::SETOGE:
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return VECC::CC_GE;
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case ISD::SETO:
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return VECC::CC_NUM;
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case ISD::SETUO:
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return VECC::CC_NAN;
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case ISD::SETUEQ:
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return VECC::CC_EQNAN;
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case ISD::SETUNE:
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return VECC::CC_NENAN;
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case ISD::SETULT:
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return VECC::CC_LNAN;
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case ISD::SETUGT:
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return VECC::CC_GNAN;
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case ISD::SETULE:
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return VECC::CC_LENAN;
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case ISD::SETUGE:
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return VECC::CC_GENAN;
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case ISD::SETTRUE:
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return VECC::CC_AT;
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}
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}
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/// getImmVal - get immediate representation of integer value
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inline static uint64_t getImmVal(const ConstantSDNode *N) {
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return N->getSExtValue();
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}
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/// getFpImmVal - get immediate representation of floating point value
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inline static uint64_t getFpImmVal(const ConstantFPSDNode *N) {
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const APInt &Imm = N->getValueAPF().bitcastToAPInt();
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uint64_t Val = Imm.getZExtValue();
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if (Imm.getBitWidth() == 32) {
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// Immediate value of float place places at higher bits on VE.
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Val <<= 32;
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}
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return Val;
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}
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//===--------------------------------------------------------------------===//
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/// VEDAGToDAGISel - VE specific code to select VE machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class VEDAGToDAGISel : public SelectionDAGISel {
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/// Subtarget - Keep a pointer to the VE Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const VESubtarget *Subtarget;
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public:
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explicit VEDAGToDAGISel(VETargetMachine &tm) : SelectionDAGISel(tm) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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Subtarget = &MF.getSubtarget<VESubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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bool selectADDRrri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRrii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRzri(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRzii(SDValue N, SDValue &Base, SDValue &Index, SDValue &Offset);
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bool selectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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bool selectADDRzi(SDValue N, SDValue &Base, SDValue &Offset);
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StringRef getPassName() const override {
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return "VE DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "VEGenDAGISel.inc"
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private:
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SDNode *getGlobalBaseReg();
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bool matchADDRrr(SDValue N, SDValue &Base, SDValue &Index);
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bool matchADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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};
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} // end anonymous namespace
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bool VEDAGToDAGISel::selectADDRrri(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (Addr.getOpcode() == ISD::FrameIndex)
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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SDValue LHS, RHS;
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if (matchADDRri(Addr, LHS, RHS)) {
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if (matchADDRrr(LHS, Base, Index)) {
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Offset = RHS;
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return true;
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}
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// Return false to try selectADDRrii.
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return false;
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}
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if (matchADDRrr(Addr, LHS, RHS)) {
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// If the input is a pair of a frame-index and a register, move a
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// frame-index to LHS. This generates MI with following operands.
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// %dest, #FI, %reg, offset
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// In the eliminateFrameIndex, above MI is converted to the following.
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// %dest, %fp, %reg, fi_offset + offset
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if (dyn_cast<FrameIndexSDNode>(RHS))
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std::swap(LHS, RHS);
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if (matchADDRri(RHS, Index, Offset)) {
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Base = LHS;
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return true;
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}
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if (matchADDRri(LHS, Base, Offset)) {
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Index = RHS;
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return true;
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}
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Base = LHS;
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Index = RHS;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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return false; // Let the reg+imm(=0) pattern catch this!
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}
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bool VEDAGToDAGISel::selectADDRrii(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (matchADDRri(Addr, Base, Offset)) {
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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Base = Addr;
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool VEDAGToDAGISel::selectADDRzri(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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// Prefer ADDRrii.
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return false;
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}
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bool VEDAGToDAGISel::selectADDRzii(SDValue Addr, SDValue &Base, SDValue &Index,
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SDValue &Offset) {
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if (dyn_cast<FrameIndexSDNode>(Addr)) {
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return false;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (auto *CN = dyn_cast<ConstantSDNode>(Addr)) {
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if (isInt<32>(CN->getSExtValue())) {
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Base = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Index = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool VEDAGToDAGISel::selectADDRri(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (matchADDRri(Addr, Base, Offset))
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return true;
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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bool VEDAGToDAGISel::selectADDRzi(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (dyn_cast<FrameIndexSDNode>(Addr))
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (auto *CN = dyn_cast<ConstantSDNode>(Addr)) {
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if (isInt<32>(CN->getSExtValue())) {
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Base = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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bool VEDAGToDAGISel::matchADDRrr(SDValue Addr, SDValue &Base, SDValue &Index) {
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if (dyn_cast<FrameIndexSDNode>(Addr))
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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; // Nothing to do here.
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} else if (Addr.getOpcode() == ISD::OR) {
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// We want to look through a transform in InstCombine and DAGCombiner that
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// turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
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if (!CurDAG->haveNoCommonBitsSet(Addr.getOperand(0), Addr.getOperand(1)))
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return false;
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} else {
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return false;
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}
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if (Addr.getOperand(0).getOpcode() == VEISD::Lo ||
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Addr.getOperand(1).getOpcode() == VEISD::Lo)
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return false; // Let the LEASL patterns catch this!
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Base = Addr.getOperand(0);
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Index = Addr.getOperand(1);
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return true;
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}
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bool VEDAGToDAGISel::matchADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) {
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auto AddrTy = Addr->getValueType(0);
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
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Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<32>(CN->getSExtValue())) {
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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// Constant offset from frame ref.
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), AddrTy);
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} else {
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Base = Addr.getOperand(0);
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}
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Offset =
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CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), MVT::i32);
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return true;
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}
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}
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return false;
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}
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void VEDAGToDAGISel::Select(SDNode *N) {
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SDLoc dl(N);
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return; // Already selected.
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}
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switch (N->getOpcode()) {
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case VEISD::GLOBAL_BASE_REG:
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ReplaceNode(N, getGlobalBaseReg());
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return;
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}
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SelectCode(N);
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}
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SDNode *VEDAGToDAGISel::getGlobalBaseReg() {
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Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG
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->getRegister(GlobalBaseReg, TLI->getPointerTy(CurDAG->getDataLayout()))
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.getNode();
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}
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/// createVEISelDag - This pass converts a legalized DAG into a
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/// VE-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createVEISelDag(VETargetMachine &TM) {
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return new VEDAGToDAGISel(TM);
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}
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