76 lines
2.7 KiB
C++
76 lines
2.7 KiB
C++
//===---------------------------- Context.h ---------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a class for holding ownership of various simulated
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/// hardware units. A Context also provides a utility routine for constructing
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/// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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/// stages.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MCA_CONTEXT_H
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#define LLVM_MCA_CONTEXT_H
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
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#include "llvm/MCA/Pipeline.h"
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#include "llvm/MCA/SourceMgr.h"
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#include <memory>
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namespace llvm {
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namespace mca {
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/// This is a convenience struct to hold the parameters necessary for creating
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/// the pre-built "default" out-of-order pipeline.
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struct PipelineOptions {
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PipelineOptions(unsigned UOPQSize, unsigned DecThr, unsigned DW, unsigned RFS,
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unsigned LQS, unsigned SQS, bool NoAlias,
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bool ShouldEnableBottleneckAnalysis = false)
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: MicroOpQueueSize(UOPQSize), DecodersThroughput(DecThr),
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DispatchWidth(DW), RegisterFileSize(RFS), LoadQueueSize(LQS),
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StoreQueueSize(SQS), AssumeNoAlias(NoAlias),
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EnableBottleneckAnalysis(ShouldEnableBottleneckAnalysis) {}
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unsigned MicroOpQueueSize;
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unsigned DecodersThroughput; // Instructions per cycle.
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unsigned DispatchWidth;
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unsigned RegisterFileSize;
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unsigned LoadQueueSize;
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unsigned StoreQueueSize;
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bool AssumeNoAlias;
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bool EnableBottleneckAnalysis;
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};
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class Context {
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SmallVector<std::unique_ptr<HardwareUnit>, 4> Hardware;
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const MCRegisterInfo &MRI;
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const MCSubtargetInfo &STI;
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public:
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Context(const MCRegisterInfo &R, const MCSubtargetInfo &S) : MRI(R), STI(S) {}
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Context(const Context &C) = delete;
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Context &operator=(const Context &C) = delete;
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const MCRegisterInfo &getMCRegisterInfo() const { return MRI; }
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const MCSubtargetInfo &getMCSubtargetInfo() const { return STI; }
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void addHardwareUnit(std::unique_ptr<HardwareUnit> H) {
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Hardware.push_back(std::move(H));
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}
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/// Construct a basic pipeline for simulating an out-of-order pipeline.
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/// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
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std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
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SourceMgr &SrcMgr);
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};
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} // namespace mca
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} // namespace llvm
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#endif // LLVM_MCA_CONTEXT_H
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