201 lines
7.5 KiB
C++
201 lines
7.5 KiB
C++
//===- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This class implements a deterministic finite automaton (DFA) based
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// packetizing mechanism for VLIW architectures. It provides APIs to
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// determine whether there exists a legal mapping of instructions to
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// functional unit assignments in a packet. The DFA is auto-generated from
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// the target's Schedule.td file.
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//
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// A DFA consists of 3 major elements: states, inputs, and transitions. For
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// the packetizing mechanism, the input is the set of instruction classes for
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// a target. The state models all possible combinations of functional unit
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// consumption for a given set of instructions in a packet. A transition
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// models the addition of an instruction to a packet. In the DFA constructed
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// by this class, if an instruction can be added to a packet, then a valid
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// transition exists from the corresponding state. Invalid transitions
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// indicate that the instruction cannot be added to the current packet.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_DFAPACKETIZER_H
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#define LLVM_CODEGEN_DFAPACKETIZER_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/ScheduleDAGMutation.h"
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#include "llvm/Support/Automaton.h"
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#include <cstdint>
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#include <map>
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#include <memory>
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#include <utility>
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#include <vector>
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namespace llvm {
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class DefaultVLIWScheduler;
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class InstrItineraryData;
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class MachineFunction;
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class MachineInstr;
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class MachineLoopInfo;
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class MCInstrDesc;
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class SUnit;
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class TargetInstrInfo;
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class DFAPacketizer {
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private:
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const InstrItineraryData *InstrItins;
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Automaton<uint64_t> A;
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/// For every itinerary, an "action" to apply to the automaton. This removes
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/// the redundancy in actions between itinerary classes.
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ArrayRef<unsigned> ItinActions;
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public:
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DFAPacketizer(const InstrItineraryData *InstrItins, Automaton<uint64_t> a,
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ArrayRef<unsigned> ItinActions)
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: InstrItins(InstrItins), A(std::move(a)), ItinActions(ItinActions) {
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// Start off with resource tracking disabled.
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A.enableTranscription(false);
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}
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// Reset the current state to make all resources available.
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void clearResources() {
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A.reset();
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}
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// Set whether this packetizer should track not just whether instructions
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// can be packetized, but also which functional units each instruction ends up
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// using after packetization.
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void setTrackResources(bool Track) {
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A.enableTranscription(Track);
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}
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// Check if the resources occupied by a MCInstrDesc are available in
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// the current state.
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bool canReserveResources(const MCInstrDesc *MID);
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// Reserve the resources occupied by a MCInstrDesc and change the current
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// state to reflect that change.
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void reserveResources(const MCInstrDesc *MID);
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// Check if the resources occupied by a machine instruction are available
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// in the current state.
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bool canReserveResources(MachineInstr &MI);
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// Reserve the resources occupied by a machine instruction and change the
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// current state to reflect that change.
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void reserveResources(MachineInstr &MI);
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// Return the resources used by the InstIdx'th instruction added to this
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// packet. The resources are returned as a bitvector of functional units.
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//
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// Note that a bundle may be packed in multiple valid ways. This function
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// returns one arbitary valid packing.
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//
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// Requires setTrackResources(true) to have been called.
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unsigned getUsedResources(unsigned InstIdx);
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const InstrItineraryData *getInstrItins() const { return InstrItins; }
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};
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// VLIWPacketizerList implements a simple VLIW packetizer using DFA. The
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// packetizer works on machine basic blocks. For each instruction I in BB,
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// the packetizer consults the DFA to see if machine resources are available
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// to execute I. If so, the packetizer checks if I depends on any instruction
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// in the current packet. If no dependency is found, I is added to current
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// packet and the machine resource is marked as taken. If any dependency is
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// found, a target API call is made to prune the dependence.
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class VLIWPacketizerList {
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protected:
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MachineFunction &MF;
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const TargetInstrInfo *TII;
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AAResults *AA;
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// The VLIW Scheduler.
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DefaultVLIWScheduler *VLIWScheduler;
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// Vector of instructions assigned to the current packet.
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std::vector<MachineInstr*> CurrentPacketMIs;
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// DFA resource tracker.
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DFAPacketizer *ResourceTracker;
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// Map: MI -> SU.
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std::map<MachineInstr*, SUnit*> MIToSUnit;
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public:
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// The AAResults parameter can be nullptr.
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VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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AAResults *AA);
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virtual ~VLIWPacketizerList();
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// Implement this API in the backend to bundle instructions.
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void PacketizeMIs(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator BeginItr,
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MachineBasicBlock::iterator EndItr);
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// Return the ResourceTracker.
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DFAPacketizer *getResourceTracker() {return ResourceTracker;}
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// addToPacket - Add MI to the current packet.
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virtual MachineBasicBlock::iterator addToPacket(MachineInstr &MI) {
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CurrentPacketMIs.push_back(&MI);
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ResourceTracker->reserveResources(MI);
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return MI;
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}
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// End the current packet and reset the state of the packetizer.
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// Overriding this function allows the target-specific packetizer
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// to perform custom finalization.
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virtual void endPacket(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI);
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// Perform initialization before packetizing an instruction. This
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// function is supposed to be overrided by the target dependent packetizer.
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virtual void initPacketizerState() {}
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// Check if the given instruction I should be ignored by the packetizer.
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virtual bool ignorePseudoInstruction(const MachineInstr &I,
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const MachineBasicBlock *MBB) {
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return false;
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}
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// Return true if instruction MI can not be packetized with any other
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// instruction, which means that MI itself is a packet.
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virtual bool isSoloInstruction(const MachineInstr &MI) { return true; }
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// Check if the packetizer should try to add the given instruction to
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// the current packet. One reasons for which it may not be desirable
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// to include an instruction in the current packet could be that it
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// would cause a stall.
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// If this function returns "false", the current packet will be ended,
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// and the instruction will be added to the next packet.
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virtual bool shouldAddToPacket(const MachineInstr &MI) { return true; }
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// Check if it is legal to packetize SUI and SUJ together.
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virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
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return false;
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}
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// Check if it is legal to prune dependece between SUI and SUJ.
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virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
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return false;
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}
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// Add a DAG mutation to be done before the packetization begins.
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void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation);
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bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
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bool UseTBAA = true) const;
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private:
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bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2,
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bool UseTBAA = true) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_DFAPACKETIZER_H
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