1198 lines
60 KiB
C
1198 lines
60 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
|
// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu future -emit-llvm %s -o - | FileCheck %s
|
|
|
|
// CHECK-LABEL: @test1(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], <16 x i8> [[VC]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__vector_quad res;
|
|
__builtin_mma_assemble_acc(&res, vc, vc, vc, vc);
|
|
*((__vector_quad *)resp) = res;
|
|
}
|
|
|
|
// CHECK-LABEL: @test2(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 0
|
|
// CHECK-NEXT: store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
|
|
// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
|
|
// CHECK-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
|
|
// CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
|
|
// CHECK-NEXT: [[TMP8:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 2
|
|
// CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 32
|
|
// CHECK-NEXT: [[TMP10:%.*]] = bitcast i8* [[TMP9]] to <16 x i8>*
|
|
// CHECK-NEXT: store <16 x i8> [[TMP8]], <16 x i8>* [[TMP10]], align 16
|
|
// CHECK-NEXT: [[TMP11:%.*]] = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } [[TMP2]], 3
|
|
// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 48
|
|
// CHECK-NEXT: [[TMP13:%.*]] = bitcast i8* [[TMP12]] to <16 x i8>*
|
|
// CHECK-NEXT: store <16 x i8> [[TMP11]], <16 x i8>* [[TMP13]], align 16
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__builtin_mma_disassemble_acc(resp, (__vector_quad*)vqp);
|
|
}
|
|
|
|
// CHECK-LABEL: @test3(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa !6
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test3(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__vector_pair res;
|
|
__builtin_vsx_assemble_pair(&res, vc, vc);
|
|
*((__vector_pair *)resp) = res;
|
|
}
|
|
|
|
// CHECK-LABEL: @test4(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <16 x i8>*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 0
|
|
// CHECK-NEXT: store <16 x i8> [[TMP4]], <16 x i8>* [[TMP3]], align 16
|
|
// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { <16 x i8>, <16 x i8> } [[TMP2]], 1
|
|
// CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, i8* [[RESP]], i64 16
|
|
// CHECK-NEXT: [[TMP7:%.*]] = bitcast i8* [[TMP6]] to <16 x i8>*
|
|
// CHECK-NEXT: store <16 x i8> [[TMP5]], <16 x i8>* [[TMP7]], align 16
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test4(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__builtin_vsx_disassemble_pair(resp, (__vector_pair*)vpp);
|
|
}
|
|
|
|
// CHECK-LABEL: @test5(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test5(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xxmtacc(&vq);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test6(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test6(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xxmfacc(&vq);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test7(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test7(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xxsetaccz(&vq);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test8(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test8(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi4ger8(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test9(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test9(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi8ger4(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test10(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test10(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi16ger2(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test11(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test11(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi16ger2s(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test12(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test12(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf16ger2(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test13(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test13(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf32ger(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test14(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test14(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf64ger(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test15(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test15(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi4ger8(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test16(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi8ger4(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test17(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test17(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi16ger2(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test18(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test18(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi16ger2s(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test19(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test19(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf16ger2(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test20(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test20(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf32ger(&vq, vc, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test21(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <256 x i1>, <256 x i1>* [[TMP0]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test21(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf64ger(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test22(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test22(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi4ger8pp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test23(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test23(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi8ger4pp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test24(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test24(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi8ger4spp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test25(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test25(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi16ger2pp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test26(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test26(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvi16ger2spp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test27(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test27(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi4ger8pp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test28(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test28(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi8ger4pp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test29(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test29(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi8ger4spp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test30(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test30(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi16ger2pp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test31(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test31(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvi16ger2spp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test32(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf16ger2pp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test33(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test33(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf16ger2pn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test34(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test34(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf16ger2np(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test35(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test35(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf16ger2nn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test36(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test36(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf16ger2pp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test37(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test37(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf16ger2pn(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test38(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test38(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf16ger2np(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test39(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test39(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf16ger2nn(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test40(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test40(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf32gerpp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test41(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test41(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf32gerpn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test42(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test42(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf32gernp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test43(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test43(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf32gernn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test44(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test44(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf32gerpp(&vq, vc, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test45(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test45(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf32gerpn(&vq, vc, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test46(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test46(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf32gernp(&vq, vc, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test47(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test47(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf32gernn(&vq, vc, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test48(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test48(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf64gerpp(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test49(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test49(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf64gerpn(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test50(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test50(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf64gernp(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test51(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test51(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvf64gernn(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test52(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test52(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf64gerpp(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test53(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test53(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf64gerpn(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test54(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test54(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf64gernp(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test55(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i8* [[VPP:%.*]] to <256 x i1>*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = load <256 x i1>, <256 x i1>* [[TMP2]], align 32, !tbaa !6
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test55(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvf64gernn(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test56(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test56(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvbf16ger2(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test57(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2(<16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test57(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvbf16ger2(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test58(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test58(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvbf16ger2pp(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test59(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test59(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvbf16ger2pn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test60(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test60(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvbf16ger2np(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test61(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvbf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test61(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_xvbf16ger2nn(&vq, vc, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test62(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pp(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test62(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvbf16ger2pp(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test63(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2pn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test63(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvbf16ger2pn(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test64(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2np(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test64(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvbf16ger2np(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test65(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, !tbaa !2
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvbf16ger2nn(<512 x i1> [[TMP1]], <16 x i8> [[VC:%.*]], <16 x i8> [[VC]], i32 0, i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP2]], <512 x i1>* [[TMP3]], align 64, !tbaa !2
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test65(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = *((__vector_pair *)vpp);
|
|
__builtin_mma_pmxvbf16ger2nn(&vq, vc, vc, 0, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test66(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP1]], i8* [[TMP2]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test66(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 0LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test67(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 [[OFFSET:%.*]]
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 [[OFFSET]]
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test67(const __vector_pair *vpp, signed long long offset, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(offset, vpp);
|
|
__builtin_vsx_stxvp(vp, offset, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test68(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 18
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 18
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test68(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(18LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 18LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test69(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 1
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 1
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test69(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(1LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 1LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test70(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 42
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 42
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test70(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(42LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 42LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test71(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VPP:%.*]], i64 128
|
|
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <256 x i1>* [[TMP0]] to i8*
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr <256 x i1>, <256 x i1>* [[VP2:%.*]], i64 128
|
|
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <256 x i1>* [[TMP3]] to i8*
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test71(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(32768LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 32768LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test72(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, i8* [[TMP0]], i64 32799
|
|
// CHECK-NEXT: [[TMP2:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP1]])
|
|
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <256 x i1>* [[VP2:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, i8* [[TMP3]], i64 32799
|
|
// CHECK-NEXT: tail call void @llvm.ppc.vsx.stxvp(<256 x i1> [[TMP2]], i8* [[TMP4]])
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test72(const __vector_pair *vpp, const __vector_pair *vp2) {
|
|
__vector_pair vp = __builtin_vsx_lxvp(32799LL, vpp);
|
|
__builtin_vsx_stxvp(vp, 32799LL, vp2);
|
|
}
|
|
|
|
// CHECK-LABEL: @test73(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, [[TBAA2:!tbaa !.*]]
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 8
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]], i32 0, i32 0)
|
|
// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, [[TBAA2]]
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test73(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = __builtin_vsx_lxvp(8LL, vpp);
|
|
__builtin_mma_pmxvf64gernn(&vq, vp, vc, 0, 0);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test74(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, [[TBAA2]]
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP2]])
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP3]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP4]], <512 x i1>* [[TMP5]], align 64, [[TBAA2]]
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test74(unsigned char *vqp, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = __builtin_vsx_lxvp(0LL, vpp);
|
|
__builtin_mma_xvf64gernp(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|
|
|
|
// CHECK-LABEL: @test75(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[VQP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: [[TMP1:%.*]] = load <512 x i1>, <512 x i1>* [[TMP0]], align 64, [[TBAA2:!tbaa !.*]]
|
|
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <256 x i1>* [[VPP:%.*]] to i8*
|
|
// CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, i8* [[TMP2]], i64 [[OFFS:%.*]]
|
|
// CHECK-NEXT: [[TMP4:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.lxvp(i8* [[TMP3]])
|
|
// CHECK-NEXT: [[TMP5:%.*]] = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> [[TMP1]], <256 x i1> [[TMP4]], <16 x i8> [[VC:%.*]])
|
|
// CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
|
|
// CHECK-NEXT: store <512 x i1> [[TMP5]], <512 x i1>* [[TMP6]], align 64, [[TBAA2]]
|
|
// CHECK-NEXT: ret void
|
|
//
|
|
void test75(unsigned char *vqp, signed long long offs, const __vector_pair *vpp, vector unsigned char vc, unsigned char *resp) {
|
|
__vector_quad vq = *((__vector_quad *)vqp);
|
|
__vector_pair vp = __builtin_vsx_lxvp(offs, vpp);
|
|
__builtin_mma_xvf64gernp(&vq, vp, vc);
|
|
*((__vector_quad *)resp) = vq;
|
|
}
|