675 lines
29 KiB
C
675 lines
29 KiB
C
// REQUIRES: nvptx-registered-target
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// RUN: %clang_cc1 -ffp-contract=off -triple nvptx-unknown-unknown -target-cpu sm_60 \
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// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
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// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP32 %s
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// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_60 \
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// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
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// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP64 %s
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// RUN: %clang_cc1 -ffp-contract=off -triple nvptx64-unknown-unknown -target-cpu sm_61 \
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// RUN: -fcuda-is-device -S -emit-llvm -o - -x cuda %s \
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// RUN: | FileCheck -check-prefix=CHECK -check-prefix=LP64 %s
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// RUN: %clang_cc1 -triple nvptx-unknown-unknown -target-cpu sm_53 \
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// RUN: -DERROR_CHECK -fcuda-is-device -S -o /dev/null -x cuda -verify %s
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#define __device__ __attribute__((device))
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#define __global__ __attribute__((global))
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#define __shared__ __attribute__((shared))
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#define __constant__ __attribute__((constant))
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__device__ int read_tid() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
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int x = __nvvm_read_ptx_sreg_tid_x();
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int y = __nvvm_read_ptx_sreg_tid_y();
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int z = __nvvm_read_ptx_sreg_tid_z();
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int w = __nvvm_read_ptx_sreg_tid_w();
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return x + y + z + w;
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}
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__device__ int read_ntid() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ntid.w()
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int x = __nvvm_read_ptx_sreg_ntid_x();
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int y = __nvvm_read_ptx_sreg_ntid_y();
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int z = __nvvm_read_ptx_sreg_ntid_z();
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int w = __nvvm_read_ptx_sreg_ntid_w();
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return x + y + z + w;
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}
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__device__ int read_ctaid() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.w()
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int x = __nvvm_read_ptx_sreg_ctaid_x();
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int y = __nvvm_read_ptx_sreg_ctaid_y();
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int z = __nvvm_read_ptx_sreg_ctaid_z();
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int w = __nvvm_read_ptx_sreg_ctaid_w();
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return x + y + z + w;
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}
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__device__ int read_nctaid() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.w()
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int x = __nvvm_read_ptx_sreg_nctaid_x();
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int y = __nvvm_read_ptx_sreg_nctaid_y();
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int z = __nvvm_read_ptx_sreg_nctaid_z();
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int w = __nvvm_read_ptx_sreg_nctaid_w();
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return x + y + z + w;
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}
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__device__ int read_ids() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.laneid()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.warpid()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nwarpid()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.smid()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.nsmid()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.gridid()
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int a = __nvvm_read_ptx_sreg_laneid();
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int b = __nvvm_read_ptx_sreg_warpid();
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int c = __nvvm_read_ptx_sreg_nwarpid();
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int d = __nvvm_read_ptx_sreg_smid();
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int e = __nvvm_read_ptx_sreg_nsmid();
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int f = __nvvm_read_ptx_sreg_gridid();
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return a + b + c + d + e + f;
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}
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__device__ int read_lanemasks() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.le()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt()
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int a = __nvvm_read_ptx_sreg_lanemask_eq();
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int b = __nvvm_read_ptx_sreg_lanemask_le();
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int c = __nvvm_read_ptx_sreg_lanemask_lt();
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int d = __nvvm_read_ptx_sreg_lanemask_ge();
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int e = __nvvm_read_ptx_sreg_lanemask_gt();
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return a + b + c + d + e;
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}
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__device__ long long read_clocks() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.clock()
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// CHECK: call i64 @llvm.nvvm.read.ptx.sreg.clock64()
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int a = __nvvm_read_ptx_sreg_clock();
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long long b = __nvvm_read_ptx_sreg_clock64();
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return a + b;
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}
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__device__ int read_pms() {
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.pm0()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.pm1()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.pm2()
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// CHECK: call i32 @llvm.nvvm.read.ptx.sreg.pm3()
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int a = __nvvm_read_ptx_sreg_pm0();
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int b = __nvvm_read_ptx_sreg_pm1();
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int c = __nvvm_read_ptx_sreg_pm2();
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int d = __nvvm_read_ptx_sreg_pm3();
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return a + b + c + d;
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}
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__device__ void sync() {
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// CHECK: call void @llvm.nvvm.bar.sync(i32 0)
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__nvvm_bar_sync(0);
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}
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// NVVM intrinsics
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// The idea is not to test all intrinsics, just that Clang is recognizing the
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// builtins defined in BuiltinsNVPTX.def
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__device__ void nvvm_math(float f1, float f2, double d1, double d2) {
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// CHECK: call float @llvm.nvvm.fmax.f
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float t1 = __nvvm_fmax_f(f1, f2);
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// CHECK: call float @llvm.nvvm.fmin.f
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float t2 = __nvvm_fmin_f(f1, f2);
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// CHECK: call float @llvm.nvvm.sqrt.rn.f
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float t3 = __nvvm_sqrt_rn_f(f1);
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// CHECK: call float @llvm.nvvm.rcp.rn.f
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float t4 = __nvvm_rcp_rn_f(f2);
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// CHECK: call float @llvm.nvvm.add.rn.f
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float t5 = __nvvm_add_rn_f(f1, f2);
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// CHECK: call double @llvm.nvvm.fmax.d
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double td1 = __nvvm_fmax_d(d1, d2);
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// CHECK: call double @llvm.nvvm.fmin.d
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double td2 = __nvvm_fmin_d(d1, d2);
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// CHECK: call double @llvm.nvvm.sqrt.rn.d
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double td3 = __nvvm_sqrt_rn_d(d1);
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// CHECK: call double @llvm.nvvm.rcp.rn.d
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double td4 = __nvvm_rcp_rn_d(d2);
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// CHECK: call void @llvm.nvvm.membar.cta()
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__nvvm_membar_cta();
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// CHECK: call void @llvm.nvvm.membar.gl()
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__nvvm_membar_gl();
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// CHECK: call void @llvm.nvvm.membar.sys()
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__nvvm_membar_sys();
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// CHECK: call void @llvm.nvvm.barrier0()
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__syncthreads();
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}
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__device__ int di;
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__shared__ int si;
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__device__ long dl;
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__shared__ long sl;
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__device__ long long dll;
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__shared__ long long sll;
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// Check for atomic intrinsics
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// CHECK-LABEL: nvvm_atom
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__device__ void nvvm_atom(float *fp, float f, double *dfp, double df, int *ip,
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int i, unsigned int *uip, unsigned ui, long *lp,
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long l, long long *llp, long long ll) {
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// CHECK: atomicrmw add
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__nvvm_atom_add_gen_i(ip, i);
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// CHECK: atomicrmw add
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__nvvm_atom_add_gen_l(&dl, l);
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// CHECK: atomicrmw add
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__nvvm_atom_add_gen_ll(&sll, ll);
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// CHECK: atomicrmw sub
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__nvvm_atom_sub_gen_i(ip, i);
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// CHECK: atomicrmw sub
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__nvvm_atom_sub_gen_l(&dl, l);
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// CHECK: atomicrmw sub
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__nvvm_atom_sub_gen_ll(&sll, ll);
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// CHECK: atomicrmw and
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__nvvm_atom_and_gen_i(ip, i);
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// CHECK: atomicrmw and
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__nvvm_atom_and_gen_l(&dl, l);
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// CHECK: atomicrmw and
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__nvvm_atom_and_gen_ll(&sll, ll);
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// CHECK: atomicrmw or
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__nvvm_atom_or_gen_i(ip, i);
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// CHECK: atomicrmw or
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__nvvm_atom_or_gen_l(&dl, l);
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// CHECK: atomicrmw or
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__nvvm_atom_or_gen_ll(&sll, ll);
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// CHECK: atomicrmw xor
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__nvvm_atom_xor_gen_i(ip, i);
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// CHECK: atomicrmw xor
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__nvvm_atom_xor_gen_l(&dl, l);
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// CHECK: atomicrmw xor
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__nvvm_atom_xor_gen_ll(&sll, ll);
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// CHECK: atomicrmw xchg
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__nvvm_atom_xchg_gen_i(ip, i);
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// CHECK: atomicrmw xchg
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__nvvm_atom_xchg_gen_l(&dl, l);
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// CHECK: atomicrmw xchg
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__nvvm_atom_xchg_gen_ll(&sll, ll);
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// CHECK: atomicrmw max i32*
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__nvvm_atom_max_gen_i(ip, i);
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// CHECK: atomicrmw umax i32*
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__nvvm_atom_max_gen_ui((unsigned int *)ip, i);
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// CHECK: atomicrmw max
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__nvvm_atom_max_gen_l(&dl, l);
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// CHECK: atomicrmw umax
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__nvvm_atom_max_gen_ul((unsigned long *)&dl, l);
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// CHECK: atomicrmw max i64*
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__nvvm_atom_max_gen_ll(&sll, ll);
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// CHECK: atomicrmw umax i64*
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__nvvm_atom_max_gen_ull((unsigned long long *)&sll, ll);
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// CHECK: atomicrmw min i32*
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__nvvm_atom_min_gen_i(ip, i);
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// CHECK: atomicrmw umin i32*
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__nvvm_atom_min_gen_ui((unsigned int *)ip, i);
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// CHECK: atomicrmw min
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__nvvm_atom_min_gen_l(&dl, l);
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// CHECK: atomicrmw umin
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__nvvm_atom_min_gen_ul((unsigned long *)&dl, l);
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// CHECK: atomicrmw min i64*
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__nvvm_atom_min_gen_ll(&sll, ll);
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// CHECK: atomicrmw umin i64*
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__nvvm_atom_min_gen_ull((unsigned long long *)&sll, ll);
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// CHECK: cmpxchg
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// CHECK-NEXT: extractvalue { i32, i1 } {{%[0-9]+}}, 0
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__nvvm_atom_cas_gen_i(ip, 0, i);
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// CHECK: cmpxchg
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// CHECK-NEXT: extractvalue { {{i32|i64}}, i1 } {{%[0-9]+}}, 0
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__nvvm_atom_cas_gen_l(&dl, 0, l);
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// CHECK: cmpxchg
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// CHECK-NEXT: extractvalue { i64, i1 } {{%[0-9]+}}, 0
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__nvvm_atom_cas_gen_ll(&sll, 0, ll);
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// CHECK: atomicrmw fadd float
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__nvvm_atom_add_gen_f(fp, f);
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// CHECK: call i32 @llvm.nvvm.atomic.load.inc.32.p0i32
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__nvvm_atom_inc_gen_ui(uip, ui);
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// CHECK: call i32 @llvm.nvvm.atomic.load.dec.32.p0i32
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__nvvm_atom_dec_gen_ui(uip, ui);
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//////////////////////////////////////////////////////////////////
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// Atomics with scope (only supported on sm_60+).
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#if ERROR_CHECK || __CUDA_ARCH__ >= 600
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// CHECK: call i32 @llvm.nvvm.atomic.add.gen.i.cta.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_cta_add_gen_i' needs target feature sm_60}}
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__nvvm_atom_cta_add_gen_i(ip, i);
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// LP32: call i32 @llvm.nvvm.atomic.add.gen.i.cta.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.add.gen.i.cta.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_cta_add_gen_l' needs target feature sm_60}}
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__nvvm_atom_cta_add_gen_l(&dl, l);
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// CHECK: call i64 @llvm.nvvm.atomic.add.gen.i.cta.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_cta_add_gen_ll' needs target feature sm_60}}
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__nvvm_atom_cta_add_gen_ll(&sll, ll);
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// CHECK: call i32 @llvm.nvvm.atomic.add.gen.i.sys.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_sys_add_gen_i' needs target feature sm_60}}
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__nvvm_atom_sys_add_gen_i(ip, i);
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// LP32: call i32 @llvm.nvvm.atomic.add.gen.i.sys.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.add.gen.i.sys.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_sys_add_gen_l' needs target feature sm_60}}
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__nvvm_atom_sys_add_gen_l(&dl, l);
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// CHECK: call i64 @llvm.nvvm.atomic.add.gen.i.sys.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_sys_add_gen_ll' needs target feature sm_60}}
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__nvvm_atom_sys_add_gen_ll(&sll, ll);
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// CHECK: call float @llvm.nvvm.atomic.add.gen.f.cta.f32.p0f32
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// expected-error@+1 {{'__nvvm_atom_cta_add_gen_f' needs target feature sm_60}}
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__nvvm_atom_cta_add_gen_f(fp, f);
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// CHECK: call double @llvm.nvvm.atomic.add.gen.f.cta.f64.p0f64
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// expected-error@+1 {{'__nvvm_atom_cta_add_gen_d' needs target feature sm_60}}
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__nvvm_atom_cta_add_gen_d(dfp, df);
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// CHECK: call float @llvm.nvvm.atomic.add.gen.f.sys.f32.p0f32
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// expected-error@+1 {{'__nvvm_atom_sys_add_gen_f' needs target feature sm_60}}
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__nvvm_atom_sys_add_gen_f(fp, f);
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// CHECK: call double @llvm.nvvm.atomic.add.gen.f.sys.f64.p0f64
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// expected-error@+1 {{'__nvvm_atom_sys_add_gen_d' needs target feature sm_60}}
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__nvvm_atom_sys_add_gen_d(dfp, df);
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// CHECK: call i32 @llvm.nvvm.atomic.exch.gen.i.cta.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_cta_xchg_gen_i' needs target feature sm_60}}
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__nvvm_atom_cta_xchg_gen_i(ip, i);
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// LP32: call i32 @llvm.nvvm.atomic.exch.gen.i.cta.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.exch.gen.i.cta.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_cta_xchg_gen_l' needs target feature sm_60}}
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__nvvm_atom_cta_xchg_gen_l(&dl, l);
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// CHECK: call i64 @llvm.nvvm.atomic.exch.gen.i.cta.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_cta_xchg_gen_ll' needs target feature sm_60}}
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__nvvm_atom_cta_xchg_gen_ll(&sll, ll);
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// CHECK: call i32 @llvm.nvvm.atomic.exch.gen.i.sys.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_sys_xchg_gen_i' needs target feature sm_60}}
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__nvvm_atom_sys_xchg_gen_i(ip, i);
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// LP32: call i32 @llvm.nvvm.atomic.exch.gen.i.sys.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.exch.gen.i.sys.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_sys_xchg_gen_l' needs target feature sm_60}}
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__nvvm_atom_sys_xchg_gen_l(&dl, l);
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// CHECK: call i64 @llvm.nvvm.atomic.exch.gen.i.sys.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_sys_xchg_gen_ll' needs target feature sm_60}}
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__nvvm_atom_sys_xchg_gen_ll(&sll, ll);
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// CHECK: call i32 @llvm.nvvm.atomic.max.gen.i.cta.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_cta_max_gen_i' needs target feature sm_60}}
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__nvvm_atom_cta_max_gen_i(ip, i);
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// CHECK: call i32 @llvm.nvvm.atomic.max.gen.i.cta.i32.p0i32
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// expected-error@+1 {{'__nvvm_atom_cta_max_gen_ui' needs target feature sm_60}}
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__nvvm_atom_cta_max_gen_ui((unsigned int *)ip, i);
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// LP32: call i32 @llvm.nvvm.atomic.max.gen.i.cta.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.max.gen.i.cta.i64.p0i64
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// expected-error@+1 {{'__nvvm_atom_cta_max_gen_l' needs target feature sm_60}}
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__nvvm_atom_cta_max_gen_l(&dl, l);
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// LP32: call i32 @llvm.nvvm.atomic.max.gen.i.cta.i32.p0i32
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// LP64: call i64 @llvm.nvvm.atomic.max.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_max_gen_ul' needs target feature sm_60}}
|
|
__nvvm_atom_cta_max_gen_ul((unsigned long *)lp, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.max.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_max_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_max_gen_ll(&sll, ll);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.max.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_max_gen_ull' needs target feature sm_60}}
|
|
__nvvm_atom_cta_max_gen_ull((unsigned long long *)llp, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.max.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_i(ip, i);
|
|
// CHECK: call i32 @llvm.nvvm.atomic.max.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_ui((unsigned int *)ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.max.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.max.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_l(&dl, l);
|
|
// LP32: call i32 @llvm.nvvm.atomic.max.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.max.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_ul' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_ul((unsigned long *)lp, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.max.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_ll(&sll, ll);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.max.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_max_gen_ull' needs target feature sm_60}}
|
|
__nvvm_atom_sys_max_gen_ull((unsigned long long *)llp, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.min.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_i(ip, i);
|
|
// CHECK: call i32 @llvm.nvvm.atomic.min.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_ui((unsigned int *)ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.min.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.min.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_l(&dl, l);
|
|
// LP32: call i32 @llvm.nvvm.atomic.min.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.min.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_ul' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_ul((unsigned long *)lp, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.min.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_ll(&sll, ll);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.min.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_min_gen_ull' needs target feature sm_60}}
|
|
__nvvm_atom_cta_min_gen_ull((unsigned long long *)llp, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.min.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_i(ip, i);
|
|
// CHECK: call i32 @llvm.nvvm.atomic.min.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_ui((unsigned int *)ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.min.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.min.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_l(&dl, l);
|
|
// LP32: call i32 @llvm.nvvm.atomic.min.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.min.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_ul' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_ul((unsigned long *)lp, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.min.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_ll(&sll, ll);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.min.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_min_gen_ull' needs target feature sm_60}}
|
|
__nvvm_atom_sys_min_gen_ull((unsigned long long *)llp, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.inc.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_inc_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_cta_inc_gen_ui((unsigned int *)ip, i);
|
|
// CHECK: call i32 @llvm.nvvm.atomic.inc.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_inc_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_sys_inc_gen_ui((unsigned int *)ip, i);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.dec.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_dec_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_cta_dec_gen_ui((unsigned int *)ip, i);
|
|
// CHECK: call i32 @llvm.nvvm.atomic.dec.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_dec_gen_ui' needs target feature sm_60}}
|
|
__nvvm_atom_sys_dec_gen_ui((unsigned int *)ip, i);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.and.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_and_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_cta_and_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.and.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.and.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_and_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_cta_and_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.and.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_and_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_and_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.and.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_and_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_and_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.and.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.and.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_and_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_and_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.and.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_and_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_and_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.or.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_or_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_cta_or_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.or.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.or.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_or_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_cta_or_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.or.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_or_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_or_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.or.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_or_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_or_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.or.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.or.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_or_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_or_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.or.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_or_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_or_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.xor.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_xor_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_cta_xor_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.xor.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.xor.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_xor_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_cta_xor_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.xor.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_xor_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_xor_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.xor.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_xor_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_xor_gen_i(ip, i);
|
|
// LP32: call i32 @llvm.nvvm.atomic.xor.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.xor.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_xor_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_xor_gen_l(&dl, l);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.xor.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_xor_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_xor_gen_ll(&sll, ll);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.cas.gen.i.cta.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_cta_cas_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_cta_cas_gen_i(ip, i, 0);
|
|
// LP32: call i32 @llvm.nvvm.atomic.cas.gen.i.cta.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.cas.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_cas_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_cta_cas_gen_l(&dl, l, 0);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.cas.gen.i.cta.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_cta_cas_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_cta_cas_gen_ll(&sll, ll, 0);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.atomic.cas.gen.i.sys.i32.p0i32
|
|
// expected-error@+1 {{'__nvvm_atom_sys_cas_gen_i' needs target feature sm_60}}
|
|
__nvvm_atom_sys_cas_gen_i(ip, i, 0);
|
|
// LP32: call i32 @llvm.nvvm.atomic.cas.gen.i.sys.i32.p0i32
|
|
// LP64: call i64 @llvm.nvvm.atomic.cas.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_cas_gen_l' needs target feature sm_60}}
|
|
__nvvm_atom_sys_cas_gen_l(&dl, l, 0);
|
|
// CHECK: call i64 @llvm.nvvm.atomic.cas.gen.i.sys.i64.p0i64
|
|
// expected-error@+1 {{'__nvvm_atom_sys_cas_gen_ll' needs target feature sm_60}}
|
|
__nvvm_atom_sys_cas_gen_ll(&sll, ll, 0);
|
|
#endif
|
|
|
|
// CHECK: ret
|
|
}
|
|
|
|
// CHECK-LABEL: nvvm_ldg
|
|
__device__ void nvvm_ldg(const void *p) {
|
|
// CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0i8(i8* {{%[0-9]+}}, i32 1)
|
|
// CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0i8(i8* {{%[0-9]+}}, i32 1)
|
|
__nvvm_ldg_c((const char *)p);
|
|
__nvvm_ldg_uc((const unsigned char *)p);
|
|
|
|
// CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0i16(i16* {{%[0-9]+}}, i32 2)
|
|
// CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0i16(i16* {{%[0-9]+}}, i32 2)
|
|
__nvvm_ldg_s((const short *)p);
|
|
__nvvm_ldg_us((const unsigned short *)p);
|
|
|
|
// CHECK: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
|
// CHECK: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
|
__nvvm_ldg_i((const int *)p);
|
|
__nvvm_ldg_ui((const unsigned int *)p);
|
|
|
|
// LP32: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
|
// LP32: call i32 @llvm.nvvm.ldg.global.i.i32.p0i32(i32* {{%[0-9]+}}, i32 4)
|
|
// LP64: call i64 @llvm.nvvm.ldg.global.i.i64.p0i64(i64* {{%[0-9]+}}, i32 8)
|
|
// LP64: call i64 @llvm.nvvm.ldg.global.i.i64.p0i64(i64* {{%[0-9]+}}, i32 8)
|
|
__nvvm_ldg_l((const long *)p);
|
|
__nvvm_ldg_ul((const unsigned long *)p);
|
|
|
|
// CHECK: call float @llvm.nvvm.ldg.global.f.f32.p0f32(float* {{%[0-9]+}}, i32 4)
|
|
__nvvm_ldg_f((const float *)p);
|
|
// CHECK: call double @llvm.nvvm.ldg.global.f.f64.p0f64(double* {{%[0-9]+}}, i32 8)
|
|
__nvvm_ldg_d((const double *)p);
|
|
|
|
// In practice, the pointers we pass to __ldg will be aligned as appropriate
|
|
// for the CUDA <type>N vector types (e.g. short4), which are not the same as
|
|
// the LLVM vector types. However, each LLVM vector type has an alignment
|
|
// less than or equal to its corresponding CUDA type, so we're OK.
|
|
//
|
|
// PTX Interoperability section 2.2: "For a vector with an even number of
|
|
// elements, its alignment is set to number of elements times the alignment of
|
|
// its member: n*alignof(t)."
|
|
|
|
// CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0v2i8(<2 x i8>* {{%[0-9]+}}, i32 2)
|
|
// CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0v2i8(<2 x i8>* {{%[0-9]+}}, i32 2)
|
|
typedef char char2 __attribute__((ext_vector_type(2)));
|
|
typedef unsigned char uchar2 __attribute__((ext_vector_type(2)));
|
|
__nvvm_ldg_c2((const char2 *)p);
|
|
__nvvm_ldg_uc2((const uchar2 *)p);
|
|
|
|
// CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0v4i8(<4 x i8>* {{%[0-9]+}}, i32 4)
|
|
// CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0v4i8(<4 x i8>* {{%[0-9]+}}, i32 4)
|
|
typedef char char4 __attribute__((ext_vector_type(4)));
|
|
typedef unsigned char uchar4 __attribute__((ext_vector_type(4)));
|
|
__nvvm_ldg_c4((const char4 *)p);
|
|
__nvvm_ldg_uc4((const uchar4 *)p);
|
|
|
|
// CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0v2i16(<2 x i16>* {{%[0-9]+}}, i32 4)
|
|
// CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0v2i16(<2 x i16>* {{%[0-9]+}}, i32 4)
|
|
typedef short short2 __attribute__((ext_vector_type(2)));
|
|
typedef unsigned short ushort2 __attribute__((ext_vector_type(2)));
|
|
__nvvm_ldg_s2((const short2 *)p);
|
|
__nvvm_ldg_us2((const ushort2 *)p);
|
|
|
|
// CHECK: call <4 x i16> @llvm.nvvm.ldg.global.i.v4i16.p0v4i16(<4 x i16>* {{%[0-9]+}}, i32 8)
|
|
// CHECK: call <4 x i16> @llvm.nvvm.ldg.global.i.v4i16.p0v4i16(<4 x i16>* {{%[0-9]+}}, i32 8)
|
|
typedef short short4 __attribute__((ext_vector_type(4)));
|
|
typedef unsigned short ushort4 __attribute__((ext_vector_type(4)));
|
|
__nvvm_ldg_s4((const short4 *)p);
|
|
__nvvm_ldg_us4((const ushort4 *)p);
|
|
|
|
// CHECK: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0v2i32(<2 x i32>* {{%[0-9]+}}, i32 8)
|
|
// CHECK: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0v2i32(<2 x i32>* {{%[0-9]+}}, i32 8)
|
|
typedef int int2 __attribute__((ext_vector_type(2)));
|
|
typedef unsigned int uint2 __attribute__((ext_vector_type(2)));
|
|
__nvvm_ldg_i2((const int2 *)p);
|
|
__nvvm_ldg_ui2((const uint2 *)p);
|
|
|
|
// CHECK: call <4 x i32> @llvm.nvvm.ldg.global.i.v4i32.p0v4i32(<4 x i32>* {{%[0-9]+}}, i32 16)
|
|
// CHECK: call <4 x i32> @llvm.nvvm.ldg.global.i.v4i32.p0v4i32(<4 x i32>* {{%[0-9]+}}, i32 16)
|
|
typedef int int4 __attribute__((ext_vector_type(4)));
|
|
typedef unsigned int uint4 __attribute__((ext_vector_type(4)));
|
|
__nvvm_ldg_i4((const int4 *)p);
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__nvvm_ldg_ui4((const uint4 *)p);
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// CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0v2i64(<2 x i64>* {{%[0-9]+}}, i32 16)
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// CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0v2i64(<2 x i64>* {{%[0-9]+}}, i32 16)
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typedef long long longlong2 __attribute__((ext_vector_type(2)));
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typedef unsigned long long ulonglong2 __attribute__((ext_vector_type(2)));
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__nvvm_ldg_ll2((const longlong2 *)p);
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__nvvm_ldg_ull2((const ulonglong2 *)p);
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// CHECK: call <2 x float> @llvm.nvvm.ldg.global.f.v2f32.p0v2f32(<2 x float>* {{%[0-9]+}}, i32 8)
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typedef float float2 __attribute__((ext_vector_type(2)));
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__nvvm_ldg_f2((const float2 *)p);
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// CHECK: call <4 x float> @llvm.nvvm.ldg.global.f.v4f32.p0v4f32(<4 x float>* {{%[0-9]+}}, i32 16)
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typedef float float4 __attribute__((ext_vector_type(4)));
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__nvvm_ldg_f4((const float4 *)p);
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// CHECK: call <2 x double> @llvm.nvvm.ldg.global.f.v2f64.p0v2f64(<2 x double>* {{%[0-9]+}}, i32 16)
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typedef double double2 __attribute__((ext_vector_type(2)));
|
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__nvvm_ldg_d2((const double2 *)p);
|
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}
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// CHECK-LABEL: nvvm_shfl
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__device__ void nvvm_shfl(int i, float f, int a, int b) {
|
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// CHECK: call i32 @llvm.nvvm.shfl.down.i32(i32
|
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__nvvm_shfl_down_i32(i, a, b);
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// CHECK: call float @llvm.nvvm.shfl.down.f32(float
|
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__nvvm_shfl_down_f32(f, a, b);
|
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// CHECK: call i32 @llvm.nvvm.shfl.up.i32(i32
|
|
__nvvm_shfl_up_i32(i, a, b);
|
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// CHECK: call float @llvm.nvvm.shfl.up.f32(float
|
|
__nvvm_shfl_up_f32(f, a, b);
|
|
// CHECK: call i32 @llvm.nvvm.shfl.bfly.i32(i32
|
|
__nvvm_shfl_bfly_i32(i, a, b);
|
|
// CHECK: call float @llvm.nvvm.shfl.bfly.f32(float
|
|
__nvvm_shfl_bfly_f32(f, a, b);
|
|
// CHECK: call i32 @llvm.nvvm.shfl.idx.i32(i32
|
|
__nvvm_shfl_idx_i32(i, a, b);
|
|
// CHECK: call float @llvm.nvvm.shfl.idx.f32(float
|
|
__nvvm_shfl_idx_f32(f, a, b);
|
|
// CHECK: ret void
|
|
}
|
|
|
|
__device__ void nvvm_vote(int pred) {
|
|
// CHECK: call i1 @llvm.nvvm.vote.all(i1
|
|
__nvvm_vote_all(pred);
|
|
// CHECK: call i1 @llvm.nvvm.vote.any(i1
|
|
__nvvm_vote_any(pred);
|
|
// CHECK: call i1 @llvm.nvvm.vote.uni(i1
|
|
__nvvm_vote_uni(pred);
|
|
// CHECK: call i32 @llvm.nvvm.vote.ballot(i1
|
|
__nvvm_vote_ballot(pred);
|
|
// CHECK: ret void
|
|
}
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