374 lines
14 KiB
C
374 lines
14 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
|
|
// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
|
|
// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
|
|
|
|
#include <arm_mve.h>
|
|
|
|
// CHECK-LABEL: @test_vcmulq_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 0, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP0]]
|
|
//
|
|
float16x8_t test_vcmulq_f16(float16x8_t a, float16x8_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq(a, b);
|
|
#else
|
|
return vcmulq_f16(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 0, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP0]]
|
|
//
|
|
float32x4_t test_vcmulq_f32(float32x4_t a, float32x4_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq(a, b);
|
|
#else
|
|
return vcmulq_f32(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 1, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP0]]
|
|
//
|
|
float16x8_t test_vcmulq_rot90_f16(float16x8_t a, float16x8_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot90(a, b);
|
|
#else
|
|
return vcmulq_rot90_f16(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 1, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP0]]
|
|
//
|
|
float32x4_t test_vcmulq_rot90_f32(float32x4_t a, float32x4_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot90(a, b);
|
|
#else
|
|
return vcmulq_rot90_f32(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 2, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP0]]
|
|
//
|
|
float16x8_t test_vcmulq_rot180_f16(float16x8_t a, float16x8_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot180(a, b);
|
|
#else
|
|
return vcmulq_rot180_f16(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 2, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP0]]
|
|
//
|
|
float32x4_t test_vcmulq_rot180_f32(float32x4_t a, float32x4_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot180(a, b);
|
|
#else
|
|
return vcmulq_rot180_f32(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.v8f16(i32 3, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP0]]
|
|
//
|
|
float16x8_t test_vcmulq_rot270_f16(float16x8_t a, float16x8_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot270(a, b);
|
|
#else
|
|
return vcmulq_rot270_f16(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.v4f32(i32 3, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP0]]
|
|
//
|
|
float32x4_t test_vcmulq_rot270_f32(float32x4_t a, float32x4_t b)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot270(a, b);
|
|
#else
|
|
return vcmulq_rot270_f32(a, b);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_m_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_m_f16(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_m_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_m_f32(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_m_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot90_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot90_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot90_m_f16(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_m_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot90_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot90_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot90_m_f32(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_m_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot180_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot180_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot180_m_f16(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_m_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot180_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot180_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot180_m_f32(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_m_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot270_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot270_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot270_m_f16(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_m_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot270_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef polymorphic
|
|
return vcmulq_rot270_m(inactive, a, b, p);
|
|
#else
|
|
return vcmulq_rot270_m_f32(inactive, a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_x_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 0, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_x(a, b, p);
|
|
#else
|
|
return vcmulq_x_f16(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_x_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_x(a, b, p);
|
|
#else
|
|
return vcmulq_x_f32(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_x_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 1, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot90_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot90_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot90_x_f16(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot90_x_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot90_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot90_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot90_x_f32(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_x_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 2, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot180_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot180_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot180_x_f16(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot180_x_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot180_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot180_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot180_x_f32(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_x_f16(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcmulq.predicated.v8f16.v8i1(i32 3, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <8 x half> [[TMP2]]
|
|
//
|
|
float16x8_t test_vcmulq_rot270_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot270_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot270_x_f16(a, b, p);
|
|
#endif
|
|
}
|
|
|
|
// CHECK-LABEL: @test_vcmulq_rot270_x_f32(
|
|
// CHECK-NEXT: entry:
|
|
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
|
|
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
|
|
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
|
|
// CHECK-NEXT: ret <4 x float> [[TMP2]]
|
|
//
|
|
float32x4_t test_vcmulq_rot270_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
|
|
{
|
|
#ifdef POLYMORPHIC
|
|
return vcmulq_rot270_x(a, b, p);
|
|
#else
|
|
return vcmulq_rot270_x_f32(a, b, p);
|
|
#endif
|
|
}
|