213 lines
6.1 KiB
C
213 lines
6.1 KiB
C
/*===---- htmintrin.h - Standard header for PowerPC HTM ---------------===*\
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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\*===----------------------------------------------------------------------===*/
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#ifndef __HTMINTRIN_H
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#define __HTMINTRIN_H
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#ifndef __HTM__
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#error "HTM instruction set not enabled"
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#endif
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#ifdef __powerpc__
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#include <stdint.h>
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typedef uint64_t texasr_t;
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typedef uint32_t texasru_t;
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typedef uint32_t texasrl_t;
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typedef uintptr_t tfiar_t;
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typedef uintptr_t tfhar_t;
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#define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
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#define _HTM_NONTRANSACTIONAL 0x0
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#define _HTM_SUSPENDED 0x1
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#define _HTM_TRANSACTIONAL 0x2
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#define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
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(((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
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#define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
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(((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
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#define _TEXASR_FAILURE_CODE(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
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#define _TEXASRU_FAILURE_CODE(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
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#define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
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#define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
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#define _TEXASR_DISALLOWED(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
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#define _TEXASRU_DISALLOWED(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
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#define _TEXASR_NESTING_OVERFLOW(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
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#define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
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#define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
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#define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
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#define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
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#define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
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#define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
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#define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
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#define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
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#define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
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#define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
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#define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
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#define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
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#define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
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#define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
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#define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
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#define _TEXASR_ABORT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
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#define _TEXASRU_ABORT(TEXASRU) \
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_TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
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#define _TEXASR_SUSPENDED(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
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#define _TEXASR_PRIVILEGE(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
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#define _TEXASR_FAILURE_SUMMARY(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
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#define _TEXASR_TFIAR_EXACT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
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#define _TEXASR_ROT(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
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#define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
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_TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
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#endif /* __powerpc */
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#ifdef __s390__
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/* Condition codes generated by tbegin */
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#define _HTM_TBEGIN_STARTED 0
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#define _HTM_TBEGIN_INDETERMINATE 1
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#define _HTM_TBEGIN_TRANSIENT 2
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#define _HTM_TBEGIN_PERSISTENT 3
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/* The abort codes below this threshold are reserved for machine use. */
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#define _HTM_FIRST_USER_ABORT_CODE 256
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/* The transaction diagnostic block is it is defined in the Principles
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of Operation chapter 5-91. */
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struct __htm_tdb {
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unsigned char format; /* 0 */
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unsigned char flags;
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unsigned char reserved1[4];
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unsigned short nesting_depth;
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unsigned long long abort_code; /* 8 */
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unsigned long long conflict_token; /* 16 */
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unsigned long long atia; /* 24 */
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unsigned char eaid; /* 32 */
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unsigned char dxc;
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unsigned char reserved2[2];
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unsigned int program_int_id;
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unsigned long long exception_id; /* 40 */
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unsigned long long bea; /* 48 */
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unsigned char reserved3[72]; /* 56 */
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unsigned long long gprs[16]; /* 128 */
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} __attribute__((__packed__, __aligned__ (8)));
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/* Helper intrinsics to retry tbegin in case of transient failure. */
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static __inline int __attribute__((__always_inline__, __nodebug__))
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__builtin_tbegin_retry_null (int __retry)
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{
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int cc, i = 0;
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while ((cc = __builtin_tbegin(0)) == _HTM_TBEGIN_TRANSIENT
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&& i++ < __retry)
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__builtin_tx_assist(i);
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return cc;
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}
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static __inline int __attribute__((__always_inline__, __nodebug__))
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__builtin_tbegin_retry_tdb (void *__tdb, int __retry)
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{
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int cc, i = 0;
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while ((cc = __builtin_tbegin(__tdb)) == _HTM_TBEGIN_TRANSIENT
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&& i++ < __retry)
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__builtin_tx_assist(i);
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return cc;
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}
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#define __builtin_tbegin_retry(tdb, retry) \
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(__builtin_constant_p(tdb == 0) && tdb == 0 ? \
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__builtin_tbegin_retry_null(retry) : \
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__builtin_tbegin_retry_tdb(tdb, retry))
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static __inline int __attribute__((__always_inline__, __nodebug__))
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__builtin_tbegin_retry_nofloat_null (int __retry)
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{
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int cc, i = 0;
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while ((cc = __builtin_tbegin_nofloat(0)) == _HTM_TBEGIN_TRANSIENT
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&& i++ < __retry)
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__builtin_tx_assist(i);
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return cc;
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}
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static __inline int __attribute__((__always_inline__, __nodebug__))
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__builtin_tbegin_retry_nofloat_tdb (void *__tdb, int __retry)
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{
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int cc, i = 0;
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while ((cc = __builtin_tbegin_nofloat(__tdb)) == _HTM_TBEGIN_TRANSIENT
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&& i++ < __retry)
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__builtin_tx_assist(i);
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return cc;
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}
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#define __builtin_tbegin_retry_nofloat(tdb, retry) \
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(__builtin_constant_p(tdb == 0) && tdb == 0 ? \
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__builtin_tbegin_retry_nofloat_null(retry) : \
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__builtin_tbegin_retry_nofloat_tdb(tdb, retry))
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#endif /* __s390__ */
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#endif /* __HTMINTRIN_H */
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