33 lines
1.5 KiB
LLVM
33 lines
1.5 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -load-store-vectorizer -S -o - %s | FileCheck %s
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
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@lds = internal addrspace(3) global [512 x float] undef, align 4
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; The original load has an implicit alignment of 4, and should not
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; increase to an align 8 load.
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; CHECK-LABEL: @load_keep_base_alignment_missing_align(
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; CHECK: load <2 x float>, <2 x float> addrspace(3)* %{{[0-9]+}}, align 4
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define amdgpu_kernel void @load_keep_base_alignment_missing_align(float addrspace(1)* %out) {
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%ptr0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 11
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%val0 = load float, float addrspace(3)* %ptr0
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%ptr1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 12
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%val1 = load float, float addrspace(3)* %ptr1
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%add = fadd float %val0, %val1
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store float %add, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: @store_keep_base_alignment_missing_align(
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; CHECK: store <2 x float> zeroinitializer, <2 x float> addrspace(3)* %{{[0-9]+}}, align 4
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define amdgpu_kernel void @store_keep_base_alignment_missing_align() {
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%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 1
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%arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 2
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store float 0.0, float addrspace(3)* %arrayidx0
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store float 0.0, float addrspace(3)* %arrayidx1
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ret void
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}
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