192 lines
9.6 KiB
ArmAsm
192 lines
9.6 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
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# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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#
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# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
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# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
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# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
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# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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lr.d t0, (t1)
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# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
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# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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lr.d.aq t1, (t2)
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# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
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# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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lr.d.rl t2, (t3)
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# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
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# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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lr.d.aqrl t3, (t4)
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# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
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# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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sc.d t6, t5, (t4)
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# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
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# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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sc.d.aq t5, t4, (t3)
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# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
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# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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sc.d.rl t4, t3, (t2)
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# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
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# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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sc.d.aqrl t3, t2, (t1)
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# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
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# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoswap.d a4, ra, (s0)
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# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)
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# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoadd.d a1, a2, (a3)
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# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)
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# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoxor.d a2, a3, (a4)
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# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)
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# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoand.d a3, a4, (a5)
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# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
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# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoor.d a4, a5, (a6)
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# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
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# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomin.d a5, a6, (a7)
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# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)
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# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomax.d s7, s6, (s5)
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# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)
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# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amominu.d s6, s5, (s4)
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# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)
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# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomaxu.d s5, s4, (s3)
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# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)
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# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoswap.d.aq a4, ra, (s0)
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# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)
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# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoadd.d.aq a1, a2, (a3)
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# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)
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# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoxor.d.aq a2, a3, (a4)
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# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)
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# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoand.d.aq a3, a4, (a5)
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# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
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# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoor.d.aq a4, a5, (a6)
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# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)
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# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomin.d.aq a5, a6, (a7)
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# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)
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# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomax.d.aq s7, s6, (s5)
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# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)
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# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amominu.d.aq s6, s5, (s4)
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# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)
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# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomaxu.d.aq s5, s4, (s3)
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# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)
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# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoswap.d.rl a4, ra, (s0)
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# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)
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# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoadd.d.rl a1, a2, (a3)
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# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)
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# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoxor.d.rl a2, a3, (a4)
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# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)
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# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoand.d.rl a3, a4, (a5)
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# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)
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# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoor.d.rl a4, a5, (a6)
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# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)
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# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomin.d.rl a5, a6, (a7)
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# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)
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# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomax.d.rl s7, s6, (s5)
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# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)
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# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amominu.d.rl s6, s5, (s4)
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# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)
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# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomaxu.d.rl s5, s4, (s3)
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# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)
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# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoswap.d.aqrl a4, ra, (s0)
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# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)
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# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoadd.d.aqrl a1, a2, (a3)
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# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)
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# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoxor.d.aqrl a2, a3, (a4)
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# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)
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# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoand.d.aqrl a3, a4, (a5)
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# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)
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# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amoor.d.aqrl a4, a5, (a6)
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# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)
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# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomin.d.aqrl a5, a6, (a7)
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# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)
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# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomax.d.aqrl s7, s6, (s5)
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# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)
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# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amominu.d.aqrl s6, s5, (s4)
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# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)
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# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
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amomaxu.d.aqrl s5, s4, (s3)
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