505 lines
22 KiB
ArmAsm
505 lines
22 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=VI
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// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
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// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire %s 2>&1 | FileCheck %s --check-prefix=NOSICI --implicit-check-not=error:
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s -check-prefix=NOVI --implicit-check-not=error:
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//===----------------------------------------------------------------------===//
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// Generic Checks for floating-point instructions (These have modifiers).
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//===----------------------------------------------------------------------===//
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// TODO: 64-bit encoding of instructions with modifiers
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// _e32 suffix
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// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
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// VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
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v_add_f32_e32 v1, v2, v3
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// src0 inline immediate
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// SICI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06]
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// VI: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x02]
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v_add_f32 v1, 1.0, v3
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// src0 negative inline immediate
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// SICI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06]
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// VI: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x02]
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v_add_f32 v1, -1.0, v3
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// src0 literal
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// SICI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42]
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// VI: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x02,0x00,0x00,0xc8,0x42]
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v_add_f32 v1, 100.0, v3
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// src0 negative literal
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// SICI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2]
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// VI: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x02,0x00,0x00,0xc8,0xc2]
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v_add_f32 v1, -100.0, v3
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//===----------------------------------------------------------------------===//
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// Generic Checks for integer instructions (These don't have modifiers).
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//===----------------------------------------------------------------------===//
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// _e32 suffix
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// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
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// VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
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v_mul_i32_i24_e32 v1, v2, v3
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// _e64 suffix
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// SICI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
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// VI: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x02,0x00]
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v_mul_i32_i24_e64 v1, v2, v3
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// src0 inline
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// SICI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
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// VI: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x0c]
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v_mul_i32_i24_e32 v1, 3, v3
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// src0 negative inline
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// SICI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
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// VI: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x0c]
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v_mul_i32_i24_e32 v1, -3, v3
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// src1 inline
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// SICI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
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// VI: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x01,0x00]
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v_mul_i32_i24_e64 v1, v2, 3
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// src1 negative inline
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// SICI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
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// VI: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x87,0x01,0x00]
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v_mul_i32_i24_e64 v1, v2, -3
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// src0 literal
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// SICI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
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// VI: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x0c,0x64,0x00,0x00,0x00]
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v_mul_i32_i24_e32 v1, 100, v3
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// src1 negative literal
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// SICI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
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// VI: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x0c,0x9c,0xff,0xff,0xff]
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v_mul_i32_i24_e32 v1, -100, v3
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//===----------------------------------------------------------------------===//
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// Checks for legal operands
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//===----------------------------------------------------------------------===//
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// src0 sgpr
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// SICI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
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// VI: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x0c]
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v_mul_i32_i24_e32 v1, s2, v3
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// src1 sgpr
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// SICI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
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// VI: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x07,0x00,0x00]
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v_mul_i32_i24_e64 v1, v2, s3
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// src0, src1 same sgpr
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// SICI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
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// VI: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x04,0x00,0x00]
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v_mul_i32_i24_e64 v1, s2, s2
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// src0 sgpr, src1 inline
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// SICI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
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// VI: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x06,0xd1,0x02,0x06,0x01,0x00]
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v_mul_i32_i24_e64 v1, s2, 3
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// src0 inline src1 sgpr
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// SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
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// VI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x06,0xd1,0x83,0x06,0x00,0x00]
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v_mul_i32_i24_e64 v1, 3, s3
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// SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
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// NOVI: error: instruction not supported on this GPU
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v_add_i32_e32 v0, vcc, 0.5, v0
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// SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
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// NOVI: error: instruction not supported on this GPU
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v_add_i32_e32 v0, vcc, 3.125, v0
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
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v_cndmask_b32 v1, v2, v3, vcc
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// GCN: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
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v_cndmask_b32_e32 v1, v2, v3, vcc
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// SICI: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
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// VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
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v_readlane_b32 s1, v2, s3
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// SICI: v_writelane_b32 v1, s2, 4 ; encoding: [0x02,0x08,0x03,0x04]
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// VI: v_writelane_b32 v1, s2, 4 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x08,0x01,0x00]
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v_writelane_b32 v1, s2, 4
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// SICI: v_writelane_b32 v2, 1, s4 ; encoding: [0x81,0x08,0x04,0x04]
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// VI: v_writelane_b32 v2, 1, s4 ; encoding: [0x02,0x00,0x8a,0xd2,0x81,0x08,0x00,0x00]
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v_writelane_b32 v2, 1, s4
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// SICI: v_writelane_b32 v255, 0xaf123456, 2 ; encoding: [0xff,0x04,0xff,0x05,0x56,0x34,0x12,0xaf]
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// NOVI: error: operands are not valid for this GPU or mode
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v_writelane_b32 v255, 0xaf123456, 2
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// SICI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
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// VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
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v_add_f32 v1, v2, v3
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// SICI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
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// VI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
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v_sub_f32 v1, v2, v3
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// SICI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
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// VI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
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v_subrev_f32 v1, v2, v3
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// SICI: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
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// NOVI: error: instruction not supported on this GPU
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v_mac_legacy_f32 v1, v2, v3
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// SICI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
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// VI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
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v_mul_legacy_f32_e32 v1, v2, v3
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// SICI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
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// VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
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v_mul_f32 v1, v2, v3
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// SICI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
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// VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
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v_mul_i32_i24_e32 v1, v2, v3
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// SICI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
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// VI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
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v_mul_hi_i32_i24_e32 v1, v2, v3
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// SICI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
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// VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
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v_mul_u32_u24_e32 v1, v2, v3
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// SICI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
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// VI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
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v_mul_hi_u32_u24_e32 v1, v2, v3
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// SICI: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
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// NOVI: error: instruction not supported on this GPU
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v_min_legacy_f32_e32 v1, v2, v3
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// SICI: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
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// NOVI: error: instruction not supported on this GPU
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v_max_legacy_f32 v1, v2, v3
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// SICI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
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// VI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
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v_min_f32_e32 v1, v2, v3
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// SICI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
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// VI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
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v_max_f32 v1, v2 v3
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// SICI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
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// VI: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
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v_min_i32_e32 v1, v2, v3
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// SICI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
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// VI: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
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v_max_i32_e32 v1, v2, v3
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// SICI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
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// VI: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
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v_min_u32_e32 v1, v2, v3
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// SICI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
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// VI: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
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v_max_u32_e32 v1, v2, v3
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// SICI: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
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// NOVI: error: instruction not supported on this GPU
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v_lshr_b32_e32 v1, v2, v3
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// SICI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
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// VI: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
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v_lshrrev_b32_e32 v1, v2, v3
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// SICI: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
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// NOVI: error: instruction not supported on this GPU
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v_ashr_i32_e32 v1, v2, v3
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// SICI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
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// VI: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
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v_ashrrev_i32_e32 v1, v2, v3
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// SICI: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
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// NOVI: error: instruction not supported on this GPU
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v_lshl_b32_e32 v1, v2, v3
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// SICI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
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// VI: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
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v_lshlrev_b32_e32 v1, v2, v3
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// SICI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
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// VI: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
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v_and_b32_e32 v1, v2, v3
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// SICI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
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// VI: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
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v_or_b32_e32 v1, v2, v3
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// SICI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
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// VI: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
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v_xor_b32_e32 v1, v2, v3
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// SICI: v_bfm_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x3c,0xd2,0x02,0x07,0x02,0x00]
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// VI: v_bfm_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x93,0xd2,0x02,0x07,0x02,0x00]
|
|
v_bfm_b32_e64 v1, v2, v3
|
|
|
|
// SICI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
|
|
// VI: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
|
|
v_mac_f32_e32 v1, v2, v3
|
|
|
|
// SICI: v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
|
|
// VI: v_madmk_f32 v1, v2, 0x42800000, v3 ; encoding: [0x02,0x07,0x02,0x2e,0x00,0x00,0x80,0x42]
|
|
v_madmk_f32 v1, v2, 64.0, v3
|
|
|
|
// SICI: v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
|
|
// VI: v_madak_f32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x30,0x00,0x00,0x80,0x42]
|
|
v_madak_f32 v1, v2, v3, 64.0
|
|
|
|
// SICI: v_bcnt_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x44,0xd2,0x02,0x07,0x02,0x00]
|
|
// VI: v_bcnt_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8b,0xd2,0x02,0x07,0x02,0x00]
|
|
v_bcnt_u32_b32_e64 v1, v2, v3
|
|
|
|
// SICI: v_mbcnt_lo_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x46,0xd2,0x02,0x07,0x02,0x00]
|
|
// VI: v_mbcnt_lo_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8c,0xd2,0x02,0x07,0x02,0x00]
|
|
v_mbcnt_lo_u32_b32_e64 v1, v2, v3
|
|
|
|
// SICI: v_mbcnt_hi_u32_b32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x48,0xd2,0x02,0x07,0x02,0x00]
|
|
// VI: v_mbcnt_hi_u32_b32 v1, v2, v3 ; encoding: [0x01,0x00,0x8d,0xd2,0x02,0x07,0x02,0x00]
|
|
v_mbcnt_hi_u32_b32_e64 v1, v2, v3
|
|
|
|
// SICI: v_add_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_add_i32_e32 v1, vcc, v2, v3
|
|
|
|
// SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_add_i32 v1, s[0:1], v2, v3
|
|
|
|
// SICI: v_add_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4a,0xd2,0x02,0x07,0x02,0x00]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_add_i32_e64 v1, s[0:1], v2, v3
|
|
|
|
// SICI: v_add_i32_e64 v1, vcc, v2, v3 ; encoding: [0x01,0x6a,0x4a,0xd2,0x02,0x07,0x02,0x00]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_add_i32_e64 v1, vcc, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_add_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
|
|
v_add_u32 v1, vcc, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_add_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x19,0xd1,0x02,0x07,0x02,0x00]
|
|
v_add_u32 v1, s[0:1], v2, v3
|
|
|
|
// SICI: v_sub_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_sub_i32 v1, vcc, v2, v3
|
|
|
|
// SICI: v_sub_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4c,0xd2,0x02,0x07,0x02,0x00]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_sub_i32 v1, s[0:1], v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_sub_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
|
|
v_sub_u32 v1, vcc, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_sub_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1a,0xd1,0x02,0x07,0x02,0x00]
|
|
v_sub_u32 v1, s[0:1], v2, v3
|
|
|
|
// SICI: v_subrev_i32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_subrev_i32 v1, vcc, v2, v3
|
|
|
|
// SICI: v_subrev_i32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x4e,0xd2,0x02,0x07,0x02,0x00]
|
|
// NOVI: error: instruction not supported on this GPU
|
|
v_subrev_i32 v1, s[0:1], v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_subrev_u32_e32 v1, vcc, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
|
|
v_subrev_u32 v1, vcc, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_subrev_u32_e64 v1, s[0:1], v2, v3 ; encoding: [0x01,0x00,0x1b,0xd1,0x02,0x07,0x02,0x00]
|
|
v_subrev_u32 v1, s[0:1], v2, v3
|
|
|
|
// SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
|
|
// VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
|
|
v_addc_u32 v1, vcc, v2, v3, vcc
|
|
|
|
// SICI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x50]
|
|
// VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
|
|
v_addc_u32_e32 v1, vcc, v2, v3, vcc
|
|
|
|
|
|
// SICI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0xaa,0x01]
|
|
// VI: v_addc_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0xaa,0x01]
|
|
v_addc_u32 v1, s[0:1], v2, v3, vcc
|
|
|
|
// SICI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
|
|
// VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
|
|
v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
|
|
|
|
// SICI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x50,0xd2,0x02,0x07,0x0a,0x00]
|
|
// VI: v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3] ; encoding: [0x01,0x00,0x1c,0xd1,0x02,0x07,0x0a,0x00]
|
|
v_addc_u32_e64 v1, s[0:1], v2, v3, s[2:3]
|
|
|
|
// SICI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x50,0xd2,0x02,0x07,0xaa,0x01]
|
|
// VI: v_addc_u32_e64 v1, vcc, v2, v3, vcc ; encoding: [0x01,0x6a,0x1c,0xd1,0x02,0x07,0xaa,0x01]
|
|
v_addc_u32_e64 v1, vcc, v2, v3, vcc
|
|
|
|
// SICI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x52]
|
|
// VI: v_subb_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3a]
|
|
v_subb_u32 v1, vcc, v2, v3, vcc
|
|
|
|
// SICI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x52,0xd2,0x02,0x07,0xaa,0x01]
|
|
// VI: v_subb_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1d,0xd1,0x02,0x07,0xaa,0x01]
|
|
v_subb_u32 v1, s[0:1], v2, v3, vcc
|
|
|
|
// SICI: v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x54]
|
|
// VI: v_subbrev_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x3c]
|
|
v_subbrev_u32 v1, vcc, v2, v3, vcc
|
|
|
|
// SICI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x54,0xd2,0x02,0x07,0xaa,0x01]
|
|
// VI: v_subbrev_u32_e64 v1, s[0:1], v2, v3, vcc ; encoding: [0x01,0x00,0x1e,0xd1,0x02,0x07,0xaa,0x01]
|
|
v_subbrev_u32 v1, s[0:1], v2, v3, vcc
|
|
|
|
// SICI: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
|
|
// VI: v_ldexp_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x88,0xd2,0x02,0x07,0x02,0x00]
|
|
v_ldexp_f32 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
|
|
// VI: v_cvt_pkaccum_u8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0xf0,0xd1,0x02,0x07,0x02,0x00]
|
|
v_cvt_pkaccum_u8_f32 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
|
|
// VI: v_cvt_pknorm_i16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x94,0xd2,0x02,0x07,0x02,0x00]
|
|
v_cvt_pknorm_i16_f32 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
|
|
// VI: v_cvt_pknorm_u16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x95,0xd2,0x02,0x07,0x02,0x00]
|
|
v_cvt_pknorm_u16_f32 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
|
|
// VI: v_cvt_pkrtz_f16_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x96,0xd2,0x02,0x07,0x02,0x00]
|
|
v_cvt_pkrtz_f16_f32 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pk_u16_u32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x60,0xd2,0x02,0x07,0x02,0x00]
|
|
// VI: v_cvt_pk_u16_u32 v1, v2, v3 ; encoding: [0x01,0x00,0x97,0xd2,0x02,0x07,0x02,0x00]
|
|
v_cvt_pk_u16_u32_e64 v1, v2, v3
|
|
|
|
// SICI: v_cvt_pk_i16_i32_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x62,0xd2,0x02,0x07,0x02,0x00]
|
|
// VI: v_cvt_pk_i16_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x98,0xd2,0x02,0x07,0x02,0x00]
|
|
v_cvt_pk_i16_i32_e64 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
|
|
v_add_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_sub_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x40]
|
|
v_sub_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_subrev_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x42]
|
|
v_subrev_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_mul_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
|
|
v_mul_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_mac_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
|
|
v_mac_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_madmk_f16 v1, v2, 0x5400, v3 ; encoding: [0x02,0x07,0x02,0x48,0x00,0x54,0x00,0x00]
|
|
v_madmk_f16 v1, v2, 64.0, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_madak_f16 v1, v2, v3, 0x5400 ; encoding: [0x02,0x07,0x02,0x4a,0x00,0x54,0x00,0x00]
|
|
v_madak_f16 v1, v2, v3, 64.0
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_add_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
|
|
v_add_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_add_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x26,0xd1,0x02,0x07,0x02,0x00]
|
|
v_add_u16 v1, v2, v3 clamp
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_sub_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
|
|
v_sub_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_sub_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x27,0xd1,0x02,0x07,0x02,0x00]
|
|
v_sub_u16 v1, v2, v3 clamp
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_subrev_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
|
|
v_subrev_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_subrev_u16_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x28,0xd1,0x02,0x07,0x02,0x00]
|
|
v_subrev_u16 v1, v2, v3 clamp
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_mul_lo_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
|
|
v_mul_lo_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_lshlrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
|
|
v_lshlrev_b16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_lshrrev_b16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
|
|
v_lshrrev_b16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_ashrrev_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
|
|
v_ashrrev_i16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_max_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
|
|
v_max_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_min_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
|
|
v_min_f16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_max_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
|
|
v_max_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_max_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
|
|
v_max_i16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_min_u16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
|
|
v_min_u16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_min_i16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x64]
|
|
v_min_i16_e32 v1, v2, v3
|
|
|
|
// NOSICI: error: instruction not supported on this GPU
|
|
// VI: v_ldexp_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x66]
|
|
v_ldexp_f16_e32 v1, v2, v3
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