llvm-for-llvmta/test/CodeGen/X86/scalar-extract.ll

21 lines
655 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+mmx | FileCheck %s
; Check that widening doesn't introduce a mmx register in this case when
; a simple load/store would suffice.
define void @foo(<2 x i16>* %A, <2 x i16>* %B) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movl (%ecx), %ecx
; CHECK-NEXT: movl %ecx, (%eax)
; CHECK-NEXT: retl
entry:
%tmp1 = load <2 x i16>, <2 x i16>* %A ; <<2 x i16>> [#uses=1]
store <2 x i16> %tmp1, <2 x i16>* %B
ret void
}