366 lines
9.5 KiB
YAML
366 lines
9.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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define i8 @zext_i1_to_i8(i1 %val) {
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%res = zext i1 %val to i8
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ret i8 %res
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}
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define i16 @zext_i1_to_i16(i1 %val) {
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%res = zext i1 %val to i16
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ret i16 %res
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}
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define i32 @zext_i1_to_i32(i1 %val) {
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%res = zext i1 %val to i32
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ret i32 %res
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}
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define i64 @zext_i1_to_i64(i1 %val) {
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%res = zext i1 %val to i64
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ret i64 %res
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}
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define i16 @zext_i8_to_i16(i8 %val) {
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%res = zext i8 %val to i16
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ret i16 %res
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}
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define i32 @zext_i8_to_i32(i8 %val) {
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%res = zext i8 %val to i32
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ret i32 %res
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}
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define i64 @zext_i8_to_i64(i8 %val) {
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%res = zext i8 %val to i64
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ret i64 %res
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}
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define i32 @zext_i16_to_i32(i16 %val) {
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%res = zext i16 %val to i32
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ret i32 %res
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}
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define i64 @zext_i16_to_i64(i16 %val) {
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%res = zext i16 %val to i64
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ret i64 %res
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}
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define i64 @zext_i32_to_i64(i32 %val) {
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%res = zext i32 %val to i64
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ret i64 %res
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}
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...
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---
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name: zext_i1_to_i8
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i1_to_i8
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
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; CHECK: $al = COPY [[AND8ri]]
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; CHECK: RET 0, implicit $al
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%1:gpr(s32) = COPY $edi
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%3:gpr(s8) = G_CONSTANT i8 1
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%4:gpr(s8) = G_TRUNC %1(s32)
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%2:gpr(s8) = G_AND %4, %3
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$al = COPY %2(s8)
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RET 0, implicit $al
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...
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---
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name: zext_i1_to_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i1_to_i16
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK: [[AND16ri8_:%[0-9]+]]:gr16 = AND16ri8 [[COPY1]], 1, implicit-def $eflags
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; CHECK: $ax = COPY [[AND16ri8_]]
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; CHECK: RET 0, implicit $ax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s16) = G_CONSTANT i16 1
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%4:gpr(s16) = G_TRUNC %1(s32)
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%2:gpr(s16) = G_AND %4, %3
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: zext_i1_to_i32
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i1_to_i32
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[COPY]], 1, implicit-def $eflags
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; CHECK: $eax = COPY [[AND32ri8_]]
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; CHECK: RET 0, implicit $eax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s32) = G_CONSTANT i32 1
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%4:gpr(s32) = COPY %1(s32)
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%2:gpr(s32) = G_AND %4, %3
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: zext_i1_to_i64
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i1_to_i64
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
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; CHECK: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
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; CHECK: $rax = COPY [[AND64ri8_]]
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; CHECK: RET 0, implicit $rax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s64) = G_CONSTANT i64 1
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%4:gpr(s64) = G_ANYEXT %1(s32)
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%2:gpr(s64) = G_AND %4, %3
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: zext_i8_to_i16
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i8_to_i16
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
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; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
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; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
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; CHECK: $ax = COPY [[COPY3]]
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; CHECK: RET 0, implicit $ax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s16) = G_CONSTANT i16 255
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%4:gpr(s16) = G_TRUNC %1(s32)
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%2:gpr(s16) = G_AND %4, %3
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: zext_i8_to_i32
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i8_to_i32
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
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; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
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; CHECK: $eax = COPY [[MOVZX32rr8_]]
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; CHECK: RET 0, implicit $eax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s32) = G_CONSTANT i32 255
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%4:gpr(s32) = COPY %1(s32)
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%2:gpr(s32) = G_AND %4, %3
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: zext_i8_to_i64
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i8_to_i64
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
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; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags
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; CHECK: $rax = COPY [[AND64ri32_]]
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; CHECK: RET 0, implicit $rax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s64) = G_CONSTANT i64 255
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%4:gpr(s64) = G_ANYEXT %1(s32)
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%2:gpr(s64) = G_AND %4, %3
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: zext_i16_to_i32
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i16_to_i32
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
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; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
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; CHECK: $eax = COPY [[MOVZX32rr16_]]
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; CHECK: RET 0, implicit $eax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s32) = G_CONSTANT i32 65535
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%4:gpr(s32) = COPY %1(s32)
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%2:gpr(s32) = G_AND %4, %3
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: zext_i16_to_i64
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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- { id: 4, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i16_to_i64
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
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; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags
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; CHECK: $rax = COPY [[AND64ri32_]]
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; CHECK: RET 0, implicit $rax
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%1:gpr(s32) = COPY $edi
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%3:gpr(s64) = G_CONSTANT i64 65535
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%4:gpr(s64) = G_ANYEXT %1(s32)
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%2:gpr(s64) = G_AND %4, %3
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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---
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name: zext_i32_to_i64
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alignment: 16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi
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; CHECK-LABEL: name: zext_i32_to_i64
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
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; CHECK: $rax = COPY [[SUBREG_TO_REG]]
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; CHECK: RET 0, implicit $rax
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%0:gpr(s32) = COPY $edi
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%1:gpr(s64) = G_ZEXT %0(s32)
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$rax = COPY %1(s64)
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RET 0, implicit $rax
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...
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