133 lines
3.3 KiB
YAML
133 lines
3.3 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=regbankselect %s -o - | FileCheck %s
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s
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--- |
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define void @test_mul_vec512() {
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ret void
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}
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define void @test_add_vec512() {
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ret void
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}
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define void @test_sub_vec512() {
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ret void
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}
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define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) {
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%r = load <16 x i32>, <16 x i32>* %p1, align 1
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ret <16 x i32> %r
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}
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define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) {
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store <16 x i32> %val, <16 x i32>* %p1, align 1
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ret void
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}
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...
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---
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name: test_mul_vec512
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# CHECK-LABEL: name: test_mul_vec512
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alignment: 16
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legalized: true
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regBankSelected: false
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = G_MUL %0, %0
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RET 0
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...
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---
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name: test_add_vec512
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# CHECK-LABEL: name: test_add_vec512
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alignment: 16
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legalized: true
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regBankSelected: false
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = G_ADD %0, %0
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RET 0
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...
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---
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name: test_sub_vec512
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# CHECK-LABEL: name: test_sub_vec512
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alignment: 16
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legalized: true
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regBankSelected: false
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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%0(<16 x s32>) = IMPLICIT_DEF
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%1(<16 x s32>) = G_SUB %0, %0
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RET 0
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...
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---
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name: test_load_v16i32_noalign
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# CHECK-LABEL: name: test_load_v16i32_noalign
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alignment: 16
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legalized: true
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regBankSelected: false
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi
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%0(p0) = COPY $rdi
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%1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
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$zmm0 = COPY %1(<16 x s32>)
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RET 0, implicit $zmm0
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...
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---
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name: test_store_v16i32_noalign
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# CHECK-LABEL: name: test_store_v16i32_noalign
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alignment: 16
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legalized: true
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regBankSelected: false
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' }
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# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' }
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $zmm0
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%0(<16 x s32>) = COPY $zmm0
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%1(p0) = COPY $rdi
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G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
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RET 0
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...
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