942 lines
35 KiB
LLVM
942 lines
35 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector compare intrinsic instructions
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;;;
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;;; Note:
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;;; We test VCMP*vvl, VCMP*vvl_v, VCMP*rvl, VCMP*rvl_v, VCMP*ivl, VCMP*ivl_v,
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;;; VCMP*vvml_v, VCMP*rvml_v, VCMP*ivml_v, PVCMP*vvl, PVCMP*vvl_v, PVCMP*rvl,
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;;; PVCMP*rvl_v, PVCMP*vvml_v, and PVCMP*rvml_v instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpul_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpul_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvl(i64 %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpul_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvl(i64 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vsvl(i64, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpul_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.l %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vsvvl(i64, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvl_imm(<256 x double> %0) {
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; CHECK-LABEL: vcmpul_vsvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v0, 8, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvl(i64 8, <256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpul_vsvvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v1, 8, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vcmpul_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vcmpul_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.l %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpul.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpul_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpul_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.l %v1, 8, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpul.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpuw_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpuw_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvl(i32 signext %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpuw_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.w %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvl(i32 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vsvl(i32, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpuw_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.w %v1, %s0, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vsvvl(i32, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvl_imm(<256 x double> %0) {
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; CHECK-LABEL: vcmpuw_vsvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v0, 8, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvl(i32 8, <256 x double> %0, i32 256)
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ret <256 x double> %2
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpuw_vsvvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v1, 8, %v0
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vcmpuw_vvvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v2, %v0, %v1, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
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; CHECK-LABEL: vcmpuw_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 128
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmpu.w %v1, %s0, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpuw.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpuw_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpuw_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmpu.w %v1, 8, %v0, %vm1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpuw.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpswsx_vvvl(<256 x double> %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpswsx_vvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmps.w.sx %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpswsx.vvvl(<256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpswsx_vvvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 128
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vcmps.w.sx %v2, %v0, %v1
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; CHECK-NEXT: lea %s16, 256
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; CHECK-NEXT: lvl %s16
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; CHECK-NEXT: vor %v0, (0)1, %v2
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; CHECK-NEXT: b.l.t (, %s10)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
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ret <256 x double> %4
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind readnone
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define fastcc <256 x double> @vcmpswsx_vsvl(i32 signext %0, <256 x double> %1) {
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; CHECK-LABEL: vcmpswsx_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vcmps.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvl(i32 %0, <256 x double> %1, i32 256)
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ret <256 x double> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vcmpswsx.vsvl(i32, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpswsx_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.w.sx %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswsx.vsvvl(i32, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vcmpswsx_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.sx %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvl(i32 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpswsx_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.sx %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vcmpswsx_vvvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.sx %v2, %v0, %v1, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vcmpswsx_vsvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.w.sx %v1, %s0, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpswsx_vsvmvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.sx %v1, 8, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vvvl(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpswzx_vvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpswzx_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvl(i32 signext %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpswzx_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.w.zx %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvl(i32 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vsvl(i32, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpswzx_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.w.zx %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vsvvl(i32, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vcmpswzx_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvl(i32 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpswzx_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vcmpswzx_vvvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v2, %v0, %v1, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: vcmpswzx_vsvmvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: and %s0, %s0, (32)0
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.w.zx %v1, %s0, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpswzx_vsvmvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.w.zx %v1, 8, %v0, %vm1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vvvl(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpsl_vvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpsl.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpsl_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.l %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vsvl(i64 %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpsl_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.l %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvl(i64 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpsl.vsvl(i64, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: vcmpsl_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: vcmps.l %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.vcmpsl.vsvvl(i64, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vsvl_imm(<256 x double> %0) {
|
|
; CHECK-LABEL: vcmpsl_vsvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.l %v0, 8, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%2 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvl(i64 8, <256 x double> %0, i32 256)
|
|
ret <256 x double> %2
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: vcmpsl_vsvvl_imm:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: vcmps.l %v1, 8, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @vcmpsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
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; CHECK-LABEL: vcmpsl_vvvmvl:
|
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; CHECK: # %bb.0:
|
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; CHECK-NEXT: lea %s0, 128
|
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; CHECK-NEXT: lvl %s0
|
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; CHECK-NEXT: vcmps.l %v2, %v0, %v1, %vm1
|
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; CHECK-NEXT: lea %s16, 256
|
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; CHECK-NEXT: lvl %s16
|
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; CHECK-NEXT: vor %v0, (0)1, %v2
|
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; CHECK-NEXT: b.l.t (, %s10)
|
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
|
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}
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|
|
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; Function Attrs: nounwind readnone
|
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declare <256 x double> @llvm.ve.vl.vcmpsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
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|
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; Function Attrs: nounwind readnone
|
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define fastcc <256 x double> @vcmpsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
|
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; CHECK-LABEL: vcmpsl_vsvmvl:
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; CHECK: # %bb.0:
|
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; CHECK-NEXT: lea %s1, 128
|
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; CHECK-NEXT: lvl %s1
|
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; CHECK-NEXT: vcmps.l %v1, %s0, %v0, %vm1
|
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; CHECK-NEXT: lea %s16, 256
|
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; CHECK-NEXT: lvl %s16
|
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; CHECK-NEXT: vor %v0, (0)1, %v1
|
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; CHECK-NEXT: b.l.t (, %s10)
|
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%5 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
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ret <256 x double> %5
|
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}
|
|
|
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; Function Attrs: nounwind readnone
|
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declare <256 x double> @llvm.ve.vl.vcmpsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
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|
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; Function Attrs: nounwind readnone
|
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define fastcc <256 x double> @vcmpsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) {
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; CHECK-LABEL: vcmpsl_vsvmvl_imm:
|
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; CHECK: # %bb.0:
|
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; CHECK-NEXT: lea %s0, 128
|
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; CHECK-NEXT: lvl %s0
|
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; CHECK-NEXT: vcmps.l %v1, 8, %v0, %vm1
|
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; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
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; CHECK-NEXT: vor %v0, (0)1, %v1
|
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; CHECK-NEXT: b.l.t (, %s10)
|
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%4 = tail call fast <256 x double> @llvm.ve.vl.vcmpsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128)
|
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ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vvvl(<256 x double> %0, <256 x double> %1) {
|
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; CHECK-LABEL: pvcmpu_vvvl:
|
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; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmpu %v0, %v0, %v1
|
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; CHECK-NEXT: b.l.t (, %s10)
|
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%3 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: pvcmpu_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmpu %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vsvl(i64 %0, <256 x double> %1) {
|
|
; CHECK-LABEL: pvcmpu_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmpu %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vsvl(i64 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vsvl(i64, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: pvcmpu_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmpu %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vsvvl(i64, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: pvcmpu_vvvMvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmpu %v2, %v0, %v1, %vm2
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmpu_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: pvcmpu_vsvMvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmpu %v1, %s0, %v0, %vm2
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.pvcmpu.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmpu.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vvvl(<256 x double> %0, <256 x double> %1) {
|
|
; CHECK-LABEL: pvcmps_vvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 256
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmps %v0, %v0, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vvvl(<256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: pvcmps_vvvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmps %v2, %v0, %v1
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vsvl(i64 %0, <256 x double> %1) {
|
|
; CHECK-LABEL: pvcmps_vsvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 256
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmps %v0, %s0, %v0
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%3 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vsvl(i64 %0, <256 x double> %1, i32 256)
|
|
ret <256 x double> %3
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vsvl(i64, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
|
|
; CHECK-LABEL: pvcmps_vsvvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmps %v1, %s0, %v0
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%4 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
|
|
ret <256 x double> %4
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vsvvl(i64, <256 x double>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: pvcmps_vvvMvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s0, 128
|
|
; CHECK-NEXT: lvl %s0
|
|
; CHECK-NEXT: pvcmps %v2, %v0, %v1, %vm2
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v2
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
|
|
|
|
; Function Attrs: nounwind readnone
|
|
define fastcc <256 x double> @pvcmps_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
|
|
; CHECK-LABEL: pvcmps_vsvMvl:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: lea %s1, 128
|
|
; CHECK-NEXT: lvl %s1
|
|
; CHECK-NEXT: pvcmps %v1, %s0, %v0, %vm2
|
|
; CHECK-NEXT: lea %s16, 256
|
|
; CHECK-NEXT: lvl %s16
|
|
; CHECK-NEXT: vor %v0, (0)1, %v1
|
|
; CHECK-NEXT: b.l.t (, %s10)
|
|
%5 = tail call fast <256 x double> @llvm.ve.vl.pvcmps.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
|
|
ret <256 x double> %5
|
|
}
|
|
|
|
; Function Attrs: nounwind readnone
|
|
declare <256 x double> @llvm.ve.vl.pvcmps.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)
|