91 lines
4.0 KiB
YAML
91 lines
4.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-none-none-eabi"
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define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_1_pred(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
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entry:
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;
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; Intentionally left blank, see the MIR sequence below.
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;
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ret <4 x float> %inactive1
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}
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attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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...
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---
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name: vpt_2_blocks_1_pred
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$q0', virtual-reg: '' }
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- { reg: '$q1', virtual-reg: '' }
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- { reg: '$q2', virtual-reg: '' }
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- { reg: '$q5', virtual-reg: '' }
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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constants: []
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body: |
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bb.0:
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liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
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; CHECK-LABEL: name: vpt_2_blocks_1_pred
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; CHECK: successors: %bb.0(0x80000000)
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; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12
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; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 {
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; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr
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; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr
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; CHECK: }
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; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 {
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr
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; CHECK: }
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; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
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; CHECK: t2B %bb.0, 14 /* CC::al */, $noreg
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renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg
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renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg
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renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr
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renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg
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renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr
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t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr
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t2B %bb.0, 14, $noreg
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...
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