341 lines
15 KiB
LLVM
341 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @zext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: zext_scaled_i16_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vldrh.u32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_scaled_i16_i32(i16* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: sext_scaled_i16_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vldrh.s32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.sext = sext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.sext
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}
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define arm_aapcs_vfpcc <4 x i32> @scaled_i32_i32(i32* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: scaled_i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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; TODO: scaled_f16_i32
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define arm_aapcs_vfpcc <4 x float> @scaled_f32_i32(i32* %base, <4 x i32>* %offptr) {
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; CHECK-LABEL: scaled_f32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @unsigned_scaled_b_i32_i16(i32* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: unsigned_scaled_b_i32_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.zext = zext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @signed_scaled_i32_i16(i32* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: signed_scaled_i32_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.s32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.sext = sext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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define arm_aapcs_vfpcc <4 x float> @a_unsigned_scaled_f32_i16(i32* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: a_unsigned_scaled_f32_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.zext = zext <4 x i16> %offs to <4 x i32>
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x float> @b_signed_scaled_f32_i16(i32* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: b_signed_scaled_f32_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.s32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.sext = sext <4 x i16> %offs to <4 x i32>
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_signed_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: zext_signed_scaled_i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.s32 q1, [r1]
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; CHECK-NEXT: vldrh.u32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.sext = sext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_signed_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: sext_signed_scaled_i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.s32 q1, [r1]
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; CHECK-NEXT: vldrh.s32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.sext = sext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.sext = sext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.sext
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: zext_unsigned_scaled_i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u32 q1, [r1]
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; CHECK-NEXT: vldrh.u32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.zext = zext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_scaled_i16_i16(i16* %base, <4 x i16>* %offptr) {
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; CHECK-LABEL: sext_unsigned_scaled_i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrh.u32 q1, [r1]
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; CHECK-NEXT: vldrh.s32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i16>, <4 x i16>* %offptr, align 2
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%offs.zext = zext <4 x i16> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.sext = sext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.sext
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}
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define arm_aapcs_vfpcc <4 x i32> @unsigned_scaled_b_i32_i8(i32* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: unsigned_scaled_b_i32_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.zext = zext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @signed_scaled_i32_i8(i32* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: signed_scaled_i32_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.s32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.sext = sext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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define arm_aapcs_vfpcc <4 x float> @a_unsigned_scaled_f32_i8(i32* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: a_unsigned_scaled_f32_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.zext = zext <4 x i8> %offs to <4 x i32>
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.zext
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x float> @b_signed_scaled_f32_i8(i32* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: b_signed_scaled_f32_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.s32 q1, [r1]
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; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.sext = sext <4 x i8> %offs to <4 x i32>
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%i32_ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs.sext
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%ptrs = bitcast <4 x i32*> %i32_ptrs to <4 x float*>
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%gather = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
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ret <4 x float> %gather
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_signed_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: zext_signed_scaled_i16_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.s32 q1, [r1]
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; CHECK-NEXT: vldrh.u32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.sext = sext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_signed_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: sext_signed_scaled_i16_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.s32 q1, [r1]
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; CHECK-NEXT: vldrh.s32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.sext = sext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.sext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.sext = sext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.sext
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_unsigned_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: zext_unsigned_scaled_i16_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u32 q1, [r1]
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; CHECK-NEXT: vldrh.u32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.zext = zext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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%gather.zext = zext <4 x i16> %gather to <4 x i32>
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ret <4 x i32> %gather.zext
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}
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|
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define arm_aapcs_vfpcc <4 x i32> @sext_unsigned_scaled_i16_i8(i16* %base, <4 x i8>* %offptr) {
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; CHECK-LABEL: sext_unsigned_scaled_i16_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrb.u32 q1, [r1]
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; CHECK-NEXT: vldrh.s32 q0, [r0, q1, uxtw #1]
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; CHECK-NEXT: bx lr
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|
entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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|
%offs.zext = zext <4 x i8> %offs to <4 x i32>
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%ptrs = getelementptr inbounds i16, i16* %base, <4 x i32> %offs.zext
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%gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> %ptrs, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
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|
%gather.sext = sext <4 x i16> %gather to <4 x i32>
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|
ret <4 x i32> %gather.sext
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <4 x i32> @scaled_i32_i32_2gep(i32* %base, <4 x i32>* %offptr) {
|
|
; CHECK-LABEL: scaled_i32_i32_2gep:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vldrw.u32 q1, [r1]
|
|
; CHECK-NEXT: vmov.i32 q0, #0x14
|
|
; CHECK-NEXT: vshl.i32 q1, q1, #2
|
|
; CHECK-NEXT: vadd.i32 q1, q1, r0
|
|
; CHECK-NEXT: vadd.i32 q1, q1, q0
|
|
; CHECK-NEXT: vldrw.u32 q0, [q1]
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
|
|
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> %offs
|
|
%ptrs2 = getelementptr inbounds i32, <4 x i32*> %ptrs, i32 5
|
|
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs2, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
|
ret <4 x i32> %gather
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <4 x i32> @scaled_i32_i32_2gep2(i32* %base, <4 x i32>* %offptr) {
|
|
; CHECK-LABEL: scaled_i32_i32_2gep2:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: adr r1, .LCPI21_0
|
|
; CHECK-NEXT: vldrw.u32 q1, [r1]
|
|
; CHECK-NEXT: vldrw.u32 q0, [r0, q1, uxtw #2]
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 4
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI21_0:
|
|
; CHECK-NEXT: .long 5 @ 0x5
|
|
; CHECK-NEXT: .long 8 @ 0x8
|
|
; CHECK-NEXT: .long 11 @ 0xb
|
|
; CHECK-NEXT: .long 14 @ 0xe
|
|
entry:
|
|
%ptrs = getelementptr inbounds i32, i32* %base, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
|
|
%ptrs2 = getelementptr inbounds i32, <4 x i32*> %ptrs, i32 5
|
|
%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs2, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
|
|
ret <4 x i32> %gather
|
|
}
|
|
|
|
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*>, i32, <4 x i1>, <4 x i8>)
|
|
declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
|
|
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
|
|
declare <4 x half> @llvm.masked.gather.v4f16.v4p0f16(<4 x half*>, i32, <4 x i1>, <4 x half>)
|
|
declare <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*>, i32, <4 x i1>, <4 x float>)
|