265 lines
12 KiB
YAML
265 lines
12 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-cp-islands %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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%struct.head_s = type { %struct.head_s*, %struct.data_s* }
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%struct.data_s = type { i16, i16 }
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define dso_local arm_aapcscc %struct.head_s* @search(%struct.head_s* readonly %list, %struct.data_s* nocapture readonly %info) local_unnamed_addr {
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entry:
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%idx = getelementptr inbounds %struct.data_s, %struct.data_s* %info, i32 0, i32 1
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%tmp = load i16, i16* %idx, align 2
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%cmp = icmp sgt i16 %tmp, -1
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br i1 %cmp, label %while.cond.preheader, label %while.cond9.preheader
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while.cond9.preheader: ; preds = %entry
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%0 = icmp eq %struct.head_s* %list, null
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br i1 %0, label %return, label %land.rhs11.lr.ph
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land.rhs11.lr.ph: ; preds = %while.cond9.preheader
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%data16143 = bitcast %struct.data_s* %info to i16*
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%tmp1 = load i16, i16* %data16143, align 2
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%conv15 = sext i16 %tmp1 to i32
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br label %land.rhs11
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while.cond.preheader: ; preds = %entry
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%1 = icmp eq %struct.head_s* %list, null
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br i1 %1, label %return, label %land.rhs.preheader
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land.rhs.preheader: ; preds = %while.cond.preheader
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br label %land.rhs
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while.body: ; preds = %land.rhs
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%next4 = bitcast %struct.head_s* %list.addr.033 to %struct.head_s**
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%tmp4 = load %struct.head_s*, %struct.head_s** %next4, align 4
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%tobool = icmp eq %struct.head_s* %tmp4, null
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br i1 %tobool, label %return, label %land.rhs
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land.rhs: ; preds = %land.rhs.preheader, %while.body
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%list.addr.033 = phi %struct.head_s* [ %tmp4, %while.body ], [ %list, %land.rhs.preheader ]
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%info2 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.033, i32 0, i32 1
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%tmp2 = load %struct.data_s*, %struct.data_s** %info2, align 4
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%idx3 = getelementptr inbounds %struct.data_s, %struct.data_s* %tmp2, i32 0, i32 1
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%tmp3 = load i16, i16* %idx3, align 2
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%cmp7 = icmp eq i16 %tmp3, %tmp
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br i1 %cmp7, label %return, label %while.body
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while.body19: ; preds = %land.rhs11
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%next205 = bitcast %struct.head_s* %list.addr.136 to %struct.head_s**
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%tmp8 = load %struct.head_s*, %struct.head_s** %next205, align 4
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%tobool10 = icmp eq %struct.head_s* %tmp8, null
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br i1 %tobool10, label %return, label %land.rhs11
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land.rhs11: ; preds = %while.body19, %land.rhs11.lr.ph
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%list.addr.136 = phi %struct.head_s* [ %list, %land.rhs11.lr.ph ], [ %tmp8, %while.body19 ]
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%info12 = getelementptr inbounds %struct.head_s, %struct.head_s* %list.addr.136, i32 0, i32 1
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%tmp5 = load %struct.data_s*, %struct.data_s** %info12, align 4
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%data166 = bitcast %struct.data_s* %tmp5 to i16*
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%tmp6 = load i16, i16* %data166, align 2
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%2 = and i16 %tmp6, 255
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%and = zext i16 %2 to i32
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%cmp16 = icmp eq i32 %and, %conv15
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br i1 %cmp16, label %return, label %while.body19
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return: ; preds = %land.rhs11, %while.body19, %land.rhs, %while.body, %while.cond.preheader, %while.cond9.preheader
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%retval.0 = phi %struct.head_s* [ null, %while.cond.preheader ], [ null, %while.cond9.preheader ], [ null, %while.body ], [ %list.addr.033, %land.rhs ], [ null, %while.body19 ], [ %list.addr.136, %land.rhs11 ]
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ret %struct.head_s* %retval.0
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}
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...
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---
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name: search
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: search
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
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; CHECK: t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.6, 13 /* CC::le */, killed $cpsr
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; CHECK: bb.1.while.cond.preheader:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r2
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: liveins: $r0, $r2
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; CHECK: renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
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; CHECK: bb.3.land.rhs:
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; CHECK: successors: %bb.5(0x04000000), %bb.4(0x7c000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
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; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
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; CHECK: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.5, 0 /* CC::eq */, killed $cpsr
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; CHECK: bb.4.while.body:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: tB %bb.3, 14 /* CC::al */, $noreg
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; CHECK: bb.5.return:
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; CHECK: liveins: $r0
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
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; CHECK: bb.6.while.cond9.preheader:
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; CHECK: successors: %bb.7(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: tB %bb.7, 14 /* CC::al */, $noreg
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; CHECK: bb.7.land.rhs11.lr.ph:
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; CHECK: successors: %bb.8(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
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; CHECK: bb.8.land.rhs11:
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; CHECK: successors: %bb.9(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
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; CHECK: renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data166, align 2)
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; CHECK: tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 8, implicit-def $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: tB %bb.9, 14 /* CC::al */, $noreg
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; CHECK: bb.9.while.body19:
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; CHECK: successors: %bb.8(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next205)
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; CHECK: tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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; CHECK: tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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; CHECK: tB %bb.8, 14 /* CC::al */, $noreg
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bb.0.entry:
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successors: %bb.2(0x50000000), %bb.1(0x30000000)
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liveins: $r0, $r1
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renamable $r2 = t2LDRSHi12 renamable $r1, 2, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx)
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t2CMPri renamable $r2, -1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 13 /* CC::le */, killed $cpsr
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bb.2.while.cond.preheader:
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successors: %bb.3(0x50000000)
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liveins: $r0, $r2
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tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 0, 4, implicit-def $itstate
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renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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t2B %bb.3, 14 /* CC::al */, $noreg
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bb.3:
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successors: %bb.4(0x80000000)
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liveins: $r0, $r2
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renamable $r1 = tUXTH killed renamable $r2, 14 /* CC::al */, $noreg
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bb.4.land.rhs:
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successors: %bb.9(0x04000000), %bb.5(0x7c000000)
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liveins: $r0, $r1
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renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info2)
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renamable $r2 = tLDRHi killed renamable $r2, 1, 14 /* CC::al */, $noreg :: (load 2 from %ir.idx3)
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tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.9, 0 /* CC::eq */, killed $cpsr
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bb.5.while.body:
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successors: %bb.4(0x7c000000)
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liveins: $r0, $r1
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renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next4)
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tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 0, 4, implicit-def $itstate
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renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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t2B %bb.4, 14 /* CC::al */, $noreg
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bb.9.return:
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liveins: $r0
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tBX_RET 14 /* CC::al */, $noreg, implicit killed $r0
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bb.1.while.cond9.preheader:
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successors: %bb.7(0x50000000)
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liveins: $r0, $r1
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tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 0, 4, implicit-def $itstate
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renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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t2B %bb.7, 14 /* CC::al */, $noreg
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bb.7.land.rhs11.lr.ph:
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successors: %bb.8(0x80000000)
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liveins: $r0, $r1
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renamable $r1 = t2LDRSHi12 killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (load 2 from %ir.data16143)
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bb.8.land.rhs11:
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successors: %bb.6(0x80000000)
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liveins: $r0, $r1
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renamable $r2 = tLDRi renamable $r0, 1, 14 /* CC::al */, $noreg :: (load 4 from %ir.info12)
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renamable $r2 = tLDRBi killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (load 1 from %ir.data166, align 2)
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tCMPr killed renamable $r2, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 0, 8, implicit-def $itstate
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tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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t2B %bb.6, 14 /* CC::al */, $noreg
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bb.6.while.body19:
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successors: %bb.8(0x7c000000)
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liveins: $r0, $r1
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renamable $r0 = tLDRi killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (load 4 from %ir.next205)
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tCMPi8 renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2IT 0, 4, implicit-def $itstate
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renamable $r0 = tMOVi8 $noreg, 0, 0 /* CC::eq */, $cpsr, implicit killed $r0, implicit $itstate
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tBX_RET 0 /* CC::eq */, killed $cpsr, implicit $r0, implicit killed $itstate
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t2B %bb.8, 14 /* CC::al */, $noreg
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...
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