llvm-for-llvmta/test/CodeGen/PowerPC/sh-overflow.mir

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# RUN: llc -O3 -mtriple=powerpc64le-unknown-linux-gnu -start-after ppc-mi-peepholes -ppc-late-peephole -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s
---
name: special_right_shift32_0
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gprc }
- { id: 1, class: gprc }
- { id: 2, class: gprc }
liveins:
- { reg: '$r3', virtual-reg: '%0' }
machineFunctionInfo: {}
body: |
bb.0.entry:
liveins: $r3
; Ensure we do not attempt to transform this into srwi $r3, $r3, 0 in the
; form specified by ISA 3.0b (rlwinm $r3, $r3, 32 - 0, 0, 31)
; CHECK-LABEL: special_right_shift32_0:
; CHECK: slwi r[[#]], r[[#]], 0
%0:gprc = COPY killed $r3
%1:gprc = LI 0
%2:gprc = SRW killed %0, killed %1
$r3 = COPY killed %2
BLR implicit $lr, implicit $rm, implicit killed $r3
...
---
name: special_right_shift64_0
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc }
- { id: 1, class: gprc }
- { id: 2, class: g8rc }
liveins:
- { reg: '$x3', virtual-reg: '%0' }
machineFunctionInfo: {}
body: |
bb.0.entry:
liveins: $x3
; Ensure we do not attempt to transform this into srdi $r3, $r3, 0 in the
; form specified by ISA 3.0b (rldicl $r3, $r3, 64 - 0, 0)
; CHECK-LABEL: special_right_shift64_0:
; CHECK: rotldi r[[#]], r[[#]], 0
%0:g8rc = COPY killed $x3
%1:gprc = LI 0
%2:g8rc = SRD killed %0, killed %1
$x3 = COPY killed %2
BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...