203 lines
5.5 KiB
LLVM
203 lines
5.5 KiB
LLVM
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; Function Attrs: nounwind readnone
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define zeroext i32 @testCTZ32(i32 signext %a) {
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entry:
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%0 = tail call i32 @llvm.cttz.i32(i32 %a, i1 false)
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ret i32 %0
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; CHECK-LABEL: testCTZ32
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; CHECK: cnttzw 3, 3
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.cttz.i32(i32, i1)
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; Function Attrs: nounwind readnone
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define zeroext i32 @testCTZ64(i64 %a) {
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entry:
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%0 = tail call i64 @llvm.cttz.i64(i64 %a, i1 false)
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%cast = trunc i64 %0 to i32
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ret i32 %cast
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; CHECK-LABEL: testCTZ64
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; CHECK: cnttzd 3, 3
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.cttz.i64(i64, i1)
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; Function Attrs: nounwind readnone
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define <16 x i8> @testVCMPNEB(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %0
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; CHECK-LABEL: testVCMPNEB
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; CHECK: vcmpneb 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.vcmpneb(<16 x i8>, <16 x i8>)
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; Function Attrs: nounwind readnone
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define <16 x i8> @testVCMPNEZB(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%0 = tail call <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %0
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; CHECK-LABEL: testVCMPNEZB
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; CHECK: vcmpnezb 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.vcmpnezb(<16 x i8>, <16 x i8>)
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; Function Attrs: nounwind readnone
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define <8 x i16> @testVCMPNEH(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCMPNEH
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; CHECK: vcmpneh 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vcmpneh(<8 x i16>, <8 x i16>)
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; Function Attrs: nounwind readnone
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define <8 x i16> @testVCMPNEZH(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%0 = tail call <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCMPNEZH
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; CHECK: vcmpnezh 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vcmpnezh(<8 x i16>, <8 x i16>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCMPNEW(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCMPNEW
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; CHECK: vcmpnew 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vcmpnew(<4 x i32>, <4 x i32>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCMPNEZW(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCMPNEZW
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; CHECK: vcmpnezw 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vcmpnezw(<4 x i32>, <4 x i32>)
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; Function Attrs: nounwind readnone
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define <16 x i8> @testVCNTTZB(<16 x i8> %a) {
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entry:
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%0 = tail call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)
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ret <16 x i8> %0
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; CHECK-LABEL: testVCNTTZB
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; CHECK: vctzb 2, 2
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}
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; Function Attrs: nounwind readnone
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define <8 x i16> @testVCNTTZH(<8 x i16> %a) {
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entry:
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%0 = tail call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)
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ret <8 x i16> %0
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; CHECK-LABEL: testVCNTTZH
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; CHECK: vctzh 2, 2
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVCNTTZW(<4 x i32> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
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ret <4 x i32> %0
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; CHECK-LABEL: testVCNTTZW
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; CHECK: vctzw 2, 2
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}
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; Function Attrs: nounwind readnone
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define <2 x i64> @testVCNTTZD(<2 x i64> %a) {
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entry:
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%0 = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
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ret <2 x i64> %0
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; CHECK-LABEL: testVCNTTZD
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; CHECK: vctzd 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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; Function Attrs: nounwind readnone
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define i32 @testVCLZLSBB(<16 x i8> %a) {
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a)
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ret i32 %0
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; CHECK-LABEL: testVCLZLSBB
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; CHECK: vclzlsbb 3, 2
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>)
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; Function Attrs: nounwind readnone
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define i32 @testVCTZLSBB(<16 x i8> %a) {
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entry:
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%0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a)
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ret i32 %0
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; CHECK-LABEL: testVCTZLSBB
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; CHECK: vctzlsbb 3, 2
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>)
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; Function Attrs: nounwind readnone
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define <4 x i32> @testVPRTYBW(<4 x i32> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: testVPRTYBW
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; CHECK: vprtybw 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>)
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; Function Attrs: nounwind readnone
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define <2 x i64> @testVPRTYBD(<2 x i64> %a) {
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entry:
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%0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a)
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ret <2 x i64> %0
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; CHECK-LABEL: testVPRTYBD
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; CHECK: vprtybd 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>)
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; Function Attrs: nounwind readnone
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define <1 x i128> @testVPRTYBQ(<1 x i128> %a) {
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entry:
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%0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a)
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ret <1 x i128> %0
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; CHECK-LABEL: testVPRTYBQ
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; CHECK: vprtybq 2, 2
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}
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; Function Attrs: nounwind readnone
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declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>)
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