99 lines
2.8 KiB
YAML
99 lines
2.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @load1_s8_to_zextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_zextLoad2_s32(i16* %px) {entry: ret void}
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define void @load1_s8_to_sextLoad1_s32(i8* %px) {entry: ret void}
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define void @load2_s16_to_sextLoad2_s32(i16* %px) {entry: ret void}
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...
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---
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name: load1_s8_to_zextLoad1_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_zextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[LBu:%[0-9]+]]:gpr32 = LBu [[COPY]], 0 :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[LBu]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(p0) = COPY $a0
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%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load 1 from %ir.px)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load2_s16_to_zextLoad2_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load2_s16_to_zextLoad2_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[LHu:%[0-9]+]]:gpr32 = LHu [[COPY]], 0 :: (load 2 from %ir.px)
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; MIPS32: $v0 = COPY [[LHu]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(p0) = COPY $a0
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%2:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load 2 from %ir.px)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load1_s8_to_sextLoad1_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load1_s8_to_sextLoad1_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[LB:%[0-9]+]]:gpr32 = LB [[COPY]], 0 :: (load 1 from %ir.px)
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; MIPS32: $v0 = COPY [[LB]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(p0) = COPY $a0
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%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load 1 from %ir.px)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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---
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name: load2_s16_to_sextLoad2_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: load2_s16_to_sextLoad2_s32
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
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; MIPS32: [[LH:%[0-9]+]]:gpr32 = LH [[COPY]], 0 :: (load 2 from %ir.px)
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; MIPS32: $v0 = COPY [[LH]]
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; MIPS32: RetRA implicit $v0
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%0:gprb(p0) = COPY $a0
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%2:gprb(s32) = G_SEXTLOAD %0(p0) :: (load 2 from %ir.px)
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$v0 = COPY %2(s32)
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RetRA implicit $v0
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...
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