llvm-for-llvmta/test/CodeGen/Mips/GlobalISel/instruction-select/fpext_and_fptrunc.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |
define void @fpext() {entry: ret void}
define void @fptrunc() {entry: ret void}
...
---
name: fpext
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $f12
; FP32-LABEL: name: fpext
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP32: [[CVT_D32_S:%[0-9]+]]:afgr64 = CVT_D32_S [[COPY]]
; FP32: $d0 = COPY [[CVT_D32_S]]
; FP32: RetRA implicit $d0
; FP64-LABEL: name: fpext
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
; FP64: [[CVT_D64_S:%[0-9]+]]:fgr64 = CVT_D64_S [[COPY]]
; FP64: $d0 = COPY [[CVT_D64_S]]
; FP64: RetRA implicit $d0
%0:fprb(s32) = COPY $f12
%1:fprb(s64) = G_FPEXT %0(s32)
$d0 = COPY %1(s64)
RetRA implicit $d0
...
---
name: fptrunc
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $d6
; FP32-LABEL: name: fptrunc
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
; FP32: [[CVT_S_D32_:%[0-9]+]]:fgr32 = CVT_S_D32 [[COPY]]
; FP32: $f0 = COPY [[CVT_S_D32_]]
; FP32: RetRA implicit $f0
; FP64-LABEL: name: fptrunc
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
; FP64: [[CVT_S_D64_:%[0-9]+]]:fgr32 = CVT_S_D64 [[COPY]]
; FP64: $f0 = COPY [[CVT_S_D64_]]
; FP64: RetRA implicit $f0
%0:fprb(s64) = COPY $d6
%1:fprb(s32) = G_FPTRUNC %0(s64)
$f0 = COPY %1(s32)
RetRA implicit $f0
...