122 lines
4.0 KiB
LLVM
122 lines
4.0 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the pipeliner doesn't assert when renaming a phi
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; that looks like: a = PHI b, a
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%s.0 = type { i32, i32*, [0 x i32], [0 x i32], [1 x i32] }
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%s.1 = type { %s.2, %s.4, %s.5 }
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%s.2 = type { %s.3 }
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%s.3 = type { i32 }
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%s.4 = type { i32 }
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%s.5 = type { [0 x i32], [0 x i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*] }
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@g0 = external global i32, align 4
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@g1 = external global %s.0, align 4
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@g2 = external global i32, align 4
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@g3 = external global i32, align 4
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@g4 = external global i32*, align 4
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define void @f0(%s.1* nocapture readonly %a0) #0 {
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b0:
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%v0 = alloca [0 x i32], align 4
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%v1 = load i32, i32* @g0, align 4
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%v2 = load i32, i32* undef, align 4
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%v3 = load i32*, i32** getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 1), align 4
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%v4 = load i32, i32* @g2, align 4
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%v5 = sub i32 0, %v4
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%v6 = getelementptr inbounds i32, i32* %v3, i32 %v5
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%v7 = load i32, i32* undef, align 4
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switch i32 %v7, label %b15 [
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i32 0, label %b1
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i32 1, label %b2
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]
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b1: ; preds = %b0
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store i32 0, i32* @g3, align 4
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br label %b2
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b2: ; preds = %b1, %b0
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%v8 = icmp eq i32 %v1, 0
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%v9 = icmp sgt i32 %v2, 0
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%v10 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 0
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%v11 = sdiv i32 %v2, 2
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%v12 = add i32 %v11, -1
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%v13 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 1
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%v14 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 %v1
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%v15 = sub i32 1, %v4
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%v16 = getelementptr inbounds i32, i32* %v3, i32 %v15
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%v17 = sdiv i32 %v2, 4
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%v18 = icmp slt i32 %v2, -3
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%v19 = add i32 %v2, -1
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%v20 = lshr i32 %v19, 2
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%v21 = mul i32 %v20, 4
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%v22 = add i32 %v21, 4
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%v23 = add i32 %v11, -2
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%v24 = add i32 %v17, 1
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%v25 = select i1 %v18, i32 1, i32 %v24
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br label %b4
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b3: ; preds = %b14
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store i32 %v25, i32* @g3, align 4
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br label %b4
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b4: ; preds = %b13, %b3, %b2
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%v26 = phi i32 [ undef, %b2 ], [ %v42, %b3 ], [ %v42, %b13 ]
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%v27 = phi i32 [ undef, %b2 ], [ 0, %b3 ], [ 0, %b13 ]
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%v28 = phi i32 [ undef, %b2 ], [ %v30, %b3 ], [ %v30, %b13 ]
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%v29 = phi i32 [ undef, %b2 ], [ %v43, %b3 ], [ %v43, %b13 ]
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%v30 = phi i32 [ undef, %b2 ], [ undef, %b3 ], [ 0, %b13 ]
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br i1 %v8, label %b6, label %b5
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b5: ; preds = %b5, %b4
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br label %b5
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b6: ; preds = %b4
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br i1 %v9, label %b8, label %b7
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b7: ; preds = %b6
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store i32 0, i32* @g3, align 4
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br label %b11
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b8: ; preds = %b6
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br i1 undef, label %b9, label %b11
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b9: ; preds = %b8
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%v31 = load i32*, i32** @g4, align 4
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br label %b10
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b10: ; preds = %b10, %b9
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%v32 = phi i32 [ %v22, %b9 ], [ %v39, %b10 ]
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%v33 = phi i32 [ %v29, %b9 ], [ %v38, %b10 ]
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%v34 = add nsw i32 %v32, %v28
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%v35 = shl i32 %v34, 1
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%v36 = getelementptr inbounds i32, i32* %v31, i32 %v35
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%v37 = load i32, i32* %v36, align 4
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%v38 = select i1 false, i32 0, i32 %v33
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%v39 = add nsw i32 %v32, 1
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store i32 %v39, i32* @g3, align 4
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%v40 = icmp slt i32 %v39, 0
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br i1 %v40, label %b10, label %b11
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b11: ; preds = %b10, %b8, %b7
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%v41 = phi i32 [ %v29, %b8 ], [ %v29, %b7 ], [ %v38, %b10 ]
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br i1 false, label %b12, label %b13
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b12: ; preds = %b11
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br label %b13
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b13: ; preds = %b12, %b11
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%v42 = load i32, i32* %v10, align 4
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%v43 = select i1 false, i32 %v41, i32 1
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br i1 %v18, label %b4, label %b14
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b14: ; preds = %b14, %b13
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br i1 false, label %b14, label %b3
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b15: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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