186 lines
9.6 KiB
LLVM
186 lines
9.6 KiB
LLVM
; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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; This version of the conv3x3 test has both loops. This test checks that the
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; inner loop has 13 packets.
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; CHECK: loop0(.LBB0_[[LOOP:.]],
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; CHECK: .LBB0_[[LOOP]]:
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK: }
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; CHECK-NOT: }
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; CHECK: }{{[ \t]*}}:endloop0
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declare <16 x i32> @llvm.hexagon.V6.vd0() #0
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
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declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #0
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declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #0
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declare <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32>, <16 x i32>, i32) #0
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #0
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declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0
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define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8* noalias nocapture readonly %a4, i32 %a5, i8* noalias nocapture %a6) local_unnamed_addr #1 {
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b0:
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%v0 = add nsw i32 %a3, -1
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%v1 = icmp sgt i32 %a3, 2
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br i1 %v1, label %b1, label %b6
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b1: ; preds = %b0
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%v2 = getelementptr inbounds i8, i8* %a6, i32 %a1
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%v3 = getelementptr inbounds i8, i8* %a0, i32 %a1
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%v4 = bitcast i8* %a4 to i32*
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%v5 = load i32, i32* %v4, align 4, !tbaa !1, !alias.scope !5, !noalias !8
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%v6 = getelementptr inbounds i8, i8* %a4, i32 4
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%v7 = bitcast i8* %v6 to i32*
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%v8 = load i32, i32* %v7, align 4, !tbaa !1, !alias.scope !5, !noalias !8
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%v9 = getelementptr inbounds i8, i8* %a4, i32 8
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%v10 = bitcast i8* %v9 to i32*
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%v11 = load i32, i32* %v10, align 4, !tbaa !1, !alias.scope !5, !noalias !8
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%v12 = sub i32 0, %a1
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%v13 = shl nsw i32 %a1, 1
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%v14 = tail call <16 x i32> @llvm.hexagon.V6.vd0() #2
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%v15 = icmp sgt i32 %a2, 0
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br label %b2
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b2: ; preds = %b5, %b1
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%v16 = phi i8* [ %v2, %b1 ], [ %v102, %b5 ]
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%v17 = phi i8* [ %v3, %b1 ], [ %v21, %b5 ]
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%v18 = phi i32 [ 1, %b1 ], [ %v103, %b5 ]
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%v19 = getelementptr inbounds i8, i8* %v17, i32 %v12
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%v20 = getelementptr inbounds i8, i8* %v17, i32 %a1
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%v21 = getelementptr inbounds i8, i8* %v17, i32 %v13
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br i1 %v15, label %b3, label %b5
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b3: ; preds = %b2
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%v22 = bitcast i8* %v21 to <16 x i32>*
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%v23 = load <16 x i32>, <16 x i32>* %v22, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v24 = getelementptr inbounds i8, i8* %v21, i32 64
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%v25 = bitcast i8* %v24 to <16 x i32>*
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%v26 = bitcast i8* %v20 to <16 x i32>*
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%v27 = load <16 x i32>, <16 x i32>* %v26, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v28 = getelementptr inbounds i8, i8* %v20, i32 64
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%v29 = bitcast i8* %v28 to <16 x i32>*
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%v30 = bitcast i8* %v17 to <16 x i32>*
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%v31 = load <16 x i32>, <16 x i32>* %v30, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v32 = getelementptr inbounds i8, i8* %v17, i32 64
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%v33 = bitcast i8* %v32 to <16 x i32>*
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%v34 = bitcast i8* %v19 to <16 x i32>*
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%v35 = load <16 x i32>, <16 x i32>* %v34, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v36 = getelementptr inbounds i8, i8* %v19, i32 64
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%v37 = bitcast i8* %v36 to <16 x i32>*
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%v38 = getelementptr inbounds i8, i8* %v16, i32 %a1
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%v39 = bitcast i8* %v38 to <16 x i32>*
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%v40 = bitcast i8* %v16 to <16 x i32>*
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br label %b4
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b4: ; preds = %b4, %b3
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%v41 = phi <16 x i32>* [ %v39, %b3 ], [ %v99, %b4 ]
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%v42 = phi <16 x i32>* [ %v40, %b3 ], [ %v84, %b4 ]
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%v43 = phi <16 x i32>* [ %v25, %b3 ], [ %v60, %b4 ]
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%v44 = phi <16 x i32>* [ %v29, %b3 ], [ %v58, %b4 ]
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%v45 = phi <16 x i32>* [ %v33, %b3 ], [ %v56, %b4 ]
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%v46 = phi <16 x i32>* [ %v37, %b3 ], [ %v54, %b4 ]
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%v47 = phi i32 [ %a2, %b3 ], [ %v100, %b4 ]
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%v48 = phi <16 x i32> [ %v35, %b3 ], [ %v55, %b4 ]
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%v49 = phi <16 x i32> [ %v31, %b3 ], [ %v57, %b4 ]
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%v50 = phi <16 x i32> [ %v27, %b3 ], [ %v59, %b4 ]
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%v51 = phi <16 x i32> [ %v23, %b3 ], [ %v61, %b4 ]
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%v52 = phi <16 x i32> [ %v14, %b3 ], [ %v82, %b4 ]
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%v53 = phi <16 x i32> [ %v14, %b3 ], [ %v97, %b4 ]
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%v54 = getelementptr inbounds <16 x i32>, <16 x i32>* %v46, i32 1
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%v55 = load <16 x i32>, <16 x i32>* %v46, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v56 = getelementptr inbounds <16 x i32>, <16 x i32>* %v45, i32 1
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%v57 = load <16 x i32>, <16 x i32>* %v45, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v58 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 1
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%v59 = load <16 x i32>, <16 x i32>* %v44, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v60 = getelementptr inbounds <16 x i32>, <16 x i32>* %v43, i32 1
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%v61 = load <16 x i32>, <16 x i32>* %v43, align 64, !tbaa !11, !alias.scope !12, !noalias !13
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%v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v55, <16 x i32> %v48, i32 4) #2
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%v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v57, <16 x i32> %v49, i32 4) #2
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%v64 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v59, <16 x i32> %v50, i32 4) #2
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%v65 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v61, <16 x i32> %v51, i32 4) #2
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%v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v48) #2
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%v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v49) #2
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%v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
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%v69 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v65, <16 x i32> %v51) #2
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%v70 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v66, i32 %v5, i32 0) #2
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%v71 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v66, i32 %v5, i32 1) #2
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%v72 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v70, <32 x i32> %v67, i32 %v8, i32 0) #2
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%v73 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v71, <32 x i32> %v67, i32 %v8, i32 1) #2
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%v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %v11, i32 0) #2
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%v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %v11, i32 1) #2
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%v76 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v75) #2
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%v77 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v75) #2
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%v78 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v76, <16 x i32> %v77, i32 %a5) #2
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%v79 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v74) #2
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%v80 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v74) #2
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%v81 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v79, <16 x i32> %v80, i32 %a5) #2
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%v82 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v78, <16 x i32> %v81) #2
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%v83 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v82, <16 x i32> %v52, i32 1) #2
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%v84 = getelementptr inbounds <16 x i32>, <16 x i32>* %v42, i32 1
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store <16 x i32> %v83, <16 x i32>* %v42, align 64, !tbaa !11, !alias.scope !14, !noalias !15
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%v85 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v67, i32 %v5, i32 0) #2
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%v86 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v67, i32 %v5, i32 1) #2
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%v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %v8, i32 0) #2
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%v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %v8, i32 1) #2
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%v89 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v87, <32 x i32> %v69, i32 %v11, i32 0) #2
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%v90 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v88, <32 x i32> %v69, i32 %v11, i32 1) #2
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%v91 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90) #2
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%v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90) #2
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%v93 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v91, <16 x i32> %v92, i32 %a5) #2
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%v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v89) #2
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%v95 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v89) #2
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%v96 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v94, <16 x i32> %v95, i32 %a5) #2
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%v97 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v93, <16 x i32> %v96) #2
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%v98 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v97, <16 x i32> %v53, i32 1) #2
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%v99 = getelementptr inbounds <16 x i32>, <16 x i32>* %v41, i32 1
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store <16 x i32> %v98, <16 x i32>* %v41, align 64, !tbaa !11, !alias.scope !14, !noalias !15
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%v100 = add nsw i32 %v47, -64
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%v101 = icmp sgt i32 %v47, 64
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br i1 %v101, label %b4, label %b5
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b5: ; preds = %b4, %b2
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%v102 = getelementptr inbounds i8, i8* %v16, i32 %v13
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%v103 = add nuw nsw i32 %v18, 2
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%v104 = icmp slt i32 %v103, %v0
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br i1 %v104, label %b2, label %b6
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b6: ; preds = %b5, %b0
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx-length64b,+hvxv62" }
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attributes #2 = { nounwind }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!6}
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!6 = distinct !{!6, !7, !"x: %a"}
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!7 = distinct !{!7, !"x"}
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!8 = !{!9, !10}
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!9 = distinct !{!9, !7, !"x: %b"}
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!10 = distinct !{!10, !7, !"x: %c"}
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!11 = !{!3, !3, i64 0}
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!12 = !{!9}
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!13 = !{!6, !10}
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!14 = !{!10}
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!15 = !{!9, !6}
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