74 lines
2.2 KiB
LLVM
74 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check if S4_subi_asl_ri is being generated correctly.
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; CHECK-LABEL: yes_sub_asl
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; FIXME: We no longer get subi_asl here.
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; XCHECK: [[REG1:(r[0-9]+)]] = sub(#0,asl([[REG1]],#1))
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; CHECK: [[REG1:(r[0-9]+)]] = asl([[REG1]],#1)
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; CHECK: = sub(#0,[[REG1]])
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; CHECK-LABEL: no_sub_asl
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; CHECK: [[REG2:(r[0-9]+)]] = asl(r{{[0-9]+}},#1)
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; CHECK: r{{[0-9]+}} = sub([[REG2]],r{{[0-9]+}})
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%struct.rtx_def = type { i16, i8 }
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@this_insn_number = external global i32, align 4
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; Function Attrs: nounwind
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define void @yes_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
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entry:
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%code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
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%0 = load i16, i16* %code, align 4
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switch i16 %0, label %return [
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i16 2, label %if.end
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i16 5, label %if.end
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]
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if.end:
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%code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
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%1 = load i16, i16* %code6, align 4
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%cmp8 = icmp eq i16 %1, 56
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%conv9 = zext i1 %cmp8 to i32
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%2 = load i32, i32* @this_insn_number, align 4
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%3 = mul i32 %2, -2
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%sub = add nsw i32 %conv9, %3
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tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
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br label %return
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return:
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ret void
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}
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declare void @reg_is_born(%struct.rtx_def*, i32) #1
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; Function Attrs: nounwind
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define void @no_sub_asl(%struct.rtx_def* %reg, %struct.rtx_def* nocapture readonly %setter) #0 {
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entry:
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%code = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %reg, i32 0, i32 0
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%0 = load i16, i16* %code, align 4
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switch i16 %0, label %return [
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i16 2, label %if.end
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i16 5, label %if.end
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]
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if.end:
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%1 = load i32, i32* @this_insn_number, align 4
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%mul = mul nsw i32 %1, 2
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%code6 = getelementptr inbounds %struct.rtx_def, %struct.rtx_def* %setter, i32 0, i32 0
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%2 = load i16, i16* %code6, align 4
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%cmp8 = icmp eq i16 %2, 56
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%conv9 = zext i1 %cmp8 to i32
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%sub = sub nsw i32 %mul, %conv9
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tail call void @reg_is_born(%struct.rtx_def* nonnull %reg, i32 %sub) #2
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br label %return
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return:
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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attributes #1 = { "target-cpu"="hexagonv5" }
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attributes #2 = { nounwind }
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