152 lines
5.8 KiB
YAML
152 lines
5.8 KiB
YAML
# RUN: llc < %s -x mir -march=hexagon -run-pass=modulo-schedule-test -pipeliner-experimental-cg=true | FileCheck %s
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# Simple check for this sanity test; ensure all instructions are in stage 0 in
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# the prolog and stage 3 in the epilog.
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# CHECK-NOT: Stage-3
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# CHECK: J2_loop0r
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# CHECK: intregs = S2_addasl_rrri %{{[0-9]+}}, %{{[0-9]+}}, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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# CHECK: intregs = L2_loadruh_io %{{[0-9]+}}, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load 2 from %ir.cgep2, !tbaa !0)
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# CHECK: intregs = S2_storerh_pi %{{[0-9]+}}, -2, %{{[0-9]+}}, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
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# CHECK: intregs = nsw A2_addi %{{[0-9]+}}, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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# CHECK: ENDLOOP0 %bb.{{[0-9]+}}, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
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# CHECK-NOT: Stage-0
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--- |
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; ModuleID = '/google/src/cloud/jmolloy/tc/google3/third_party/llvm/llvm/test/CodeGen/Hexagon/swp-phi-start.ll'
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source_filename = "/google/src/cloud/jmolloy/tc/google3/third_party/llvm/llvm/test/CodeGen/Hexagon/swp-phi-start.ll"
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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; Function Attrs: nounwind
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define void @f0(i32 %a0, i16* nocapture %a1) #0 {
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b0:
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br i1 undef, label %b1, label %b2.preheader
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b1: ; preds = %b0
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br i1 undef, label %b3, label %b2.preheader
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b2.preheader: ; preds = %b0, %b1
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%cgep = getelementptr i16, i16* %a1, i32 undef
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br label %b2
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b2: ; preds = %b2.preheader, %b2
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%lsr.iv = phi i16* [ %cgep, %b2.preheader ], [ %cgep3, %b2 ]
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%v1 = phi i32 [ %v7, %b2 ], [ undef, %b2.preheader ]
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%v2 = phi i32 [ %v1, %b2 ], [ %a0, %b2.preheader ]
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%v3 = add nsw i32 %v2, -2
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%cgep2 = getelementptr inbounds i16, i16* %a1, i32 %v3
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%v5 = load i16, i16* %cgep2, align 2, !tbaa !0
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store i16 %v5, i16* %lsr.iv, align 2, !tbaa !0
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%v7 = add nsw i32 %v1, -1
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%v8 = icmp sgt i32 %v7, 0
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%cgep3 = getelementptr i16, i16* %lsr.iv, i32 -1
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br i1 %v8, label %b2, label %b3
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b3: ; preds = %b2, %b1
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"short", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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...
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---
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name: f0
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: intregs, preferred-register: '' }
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- { id: 1, class: intregs, preferred-register: '' }
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- { id: 2, class: intregs, preferred-register: '' }
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- { id: 3, class: intregs, preferred-register: '' }
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- { id: 4, class: intregs, preferred-register: '' }
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- { id: 5, class: intregs, preferred-register: '' }
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- { id: 6, class: intregs, preferred-register: '' }
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- { id: 7, class: intregs, preferred-register: '' }
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- { id: 8, class: predregs, preferred-register: '' }
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- { id: 9, class: predregs, preferred-register: '' }
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- { id: 10, class: intregs, preferred-register: '' }
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- { id: 11, class: intregs, preferred-register: '' }
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- { id: 12, class: intregs, preferred-register: '' }
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- { id: 13, class: predregs, preferred-register: '' }
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- { id: 14, class: intregs, preferred-register: '' }
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liveins:
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- { reg: '$r0', virtual-reg: '%6' }
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- { reg: '$r1', virtual-reg: '%7' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.b0:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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liveins: $r0, $r1
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%7:intregs = COPY $r1
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%6:intregs = COPY $r0
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%8:predregs = IMPLICIT_DEF
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J2_jumpt %8, %bb.2, implicit-def dead $pc
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J2_jump %bb.1, implicit-def dead $pc
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bb.1.b1:
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successors: %bb.4(0x40000000), %bb.2(0x40000000)
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%9:predregs = IMPLICIT_DEF
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J2_jumpt %9, %bb.4, implicit-def dead $pc
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J2_jump %bb.2, implicit-def dead $pc
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bb.2.b2.preheader:
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successors: %bb.3(0x80000000)
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%10:intregs = IMPLICIT_DEF
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%14:intregs = COPY %10
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J2_loop0r %bb.3, %14, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
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bb.3.b2 (address-taken):
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successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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%1:intregs = PHI %7, %bb.2, %5, %bb.3, post-instr-symbol <mcsymbol Stage-3_Cycle-0>
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%2:intregs = PHI %10, %bb.2, %4, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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%3:intregs = PHI %6, %bb.2, %2, %bb.3, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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%11:intregs = S2_addasl_rrri %7, %3, 1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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%12:intregs = L2_loadruh_io %11, -4, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (load 2 from %ir.cgep2, !tbaa !0)
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%5:intregs = S2_storerh_pi %1, -2, %12, post-instr-symbol <mcsymbol Stage-3_Cycle-0> :: (store 2 into %ir.lsr.iv, !tbaa !0)
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%4:intregs = nsw A2_addi %2, -1, post-instr-symbol <mcsymbol Stage-0_Cycle-0>
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ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
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J2_jump %bb.4, implicit-def dead $pc
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bb.4.b3:
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PS_jmpret $r31, implicit-def dead $pc
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...
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