136 lines
2.5 KiB
LLVM
136 lines
2.5 KiB
LLVM
; RUN: llc -march=hexagon -O3 -hexagon-small-data-threshold=0 < %s | FileCheck %s
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; Check that absolute loads are generated for 64-bit
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target triple = "hexagon-unknown--elf"
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@g0 = external global i8, align 8
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@g1 = external global i16, align 8
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@g2 = external global i32, align 8
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@g3 = external global i64, align 8
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; CHECK-LABEL: f0:
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; CHECK: = memd(##441656)
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define i64 @f0() #0 {
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b0:
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%v0 = load volatile i64, i64* inttoptr (i32 441656 to i64*)
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ret i64 %v0
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}
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; CHECK-LABEL: f1:
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; CHECK: = memw(##441656)
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define i64 @f1() #0 {
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b0:
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%v0 = load volatile i32, i32* inttoptr (i32 441656 to i32*)
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%v1 = sext i32 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f2:
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; CHECK: = memw(##441656)
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define i64 @f2() #0 {
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b0:
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%v0 = load volatile i32, i32* inttoptr (i32 441656 to i32*)
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%v1 = zext i32 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f3:
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; CHECK: = memh(##441656)
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define i64 @f3() #0 {
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b0:
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%v0 = load volatile i16, i16* inttoptr (i32 441656 to i16*)
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%v1 = sext i16 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f4:
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; CHECK: = memuh(##441656)
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define i64 @f4() #0 {
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b0:
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%v0 = load volatile i16, i16* inttoptr (i32 441656 to i16*)
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%v1 = zext i16 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f5:
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; CHECK: = memb(##441656)
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define i64 @f5() #0 {
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b0:
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%v0 = load volatile i8, i8* inttoptr (i32 441656 to i8*)
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%v1 = sext i8 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f6:
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; CHECK: = memub(##441656)
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define i64 @f6() #0 {
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b0:
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%v0 = load volatile i8, i8* inttoptr (i32 441656 to i8*)
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%v1 = zext i8 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f7:
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; CHECK: = memd(##g3)
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define i64 @f7() #0 {
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b0:
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%v0 = load volatile i64, i64* @g3
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ret i64 %v0
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}
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; CHECK-LABEL: f8:
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; CHECK: = memw(##g2)
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define i64 @f8() #0 {
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b0:
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%v0 = load volatile i32, i32* @g2
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%v1 = sext i32 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f9:
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; CHECK: = memw(##g2)
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define i64 @f9() #0 {
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b0:
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%v0 = load volatile i32, i32* @g2
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%v1 = zext i32 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f10:
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; CHECK: = memh(##g1)
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define i64 @f10() #0 {
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b0:
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%v0 = load volatile i16, i16* @g1
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%v1 = sext i16 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f11:
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; CHECK: = memuh(##g1)
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define i64 @f11() #0 {
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b0:
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%v0 = load volatile i16, i16* @g1
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%v1 = zext i16 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f12:
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; CHECK: = memb(##g0)
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define i64 @f12() #0 {
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b0:
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%v0 = load volatile i8, i8* @g0
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%v1 = sext i8 %v0 to i64
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ret i64 %v1
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}
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; CHECK-LABEL: f13:
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; CHECK: = memub(##g0)
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define i64 @f13() #0 {
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b0:
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%v0 = load volatile i8, i8* @g0
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%v1 = zext i8 %v0 to i64
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ret i64 %v1
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}
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attributes #0 = { nounwind }
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