38 lines
1.2 KiB
LLVM
38 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Test that the compiler doesn't assert because the live interval information
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; isn't updated correctly during the Hexagon Expand Condsets pass. The pass
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; wasn't updating the information when converting a mux with the same operands
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; into a copy. When this occurs, the pass needs to update the liveness
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; information for the predicate register, which is removed.
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define void @f0(i32 %a0) unnamed_addr {
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b0:
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%v0 = or i32 undef, %a0
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%v1 = or i32 undef, %v0
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br label %b1
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b1: ; preds = %b3, %b0
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%v2 = phi i32 [ %v9, %b3 ], [ 0, %b0 ]
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%v3 = phi i32 [ 0, %b3 ], [ %v1, %b0 ]
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%v4 = srem i32 %v2, 4
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%v5 = icmp eq i32 %v4, 0
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%v6 = select i1 %v5, i32 %v1, i32 %v3
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%v7 = shl i32 %v6, 8
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%v8 = add i32 0, %v7
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br i1 undef, label %b2, label %b3
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b2: ; preds = %b1
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store i32 %v8, i32* undef, align 4
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br label %b3
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b3: ; preds = %b2, %b1
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%v9 = add nuw nsw i32 %v2, 1
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%v10 = icmp slt i32 %v9, undef
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br i1 %v10, label %b1, label %b4
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b4: ; preds = %b3
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unreachable
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}
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