28 lines
1.1 KiB
LLVM
28 lines
1.1 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
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; is compiles without errors.
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; CHECK: valign
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; CHECK: vshuff
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target triple = "hexagon"
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0
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declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0
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define void @fred(<64 x i16>* %a0, <32 x i32>* %a1) #1 {
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entry:
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%t0 = bitcast <64 x i16> zeroinitializer to <32 x i32>
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%t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2)
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%t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2)
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%t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)
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store <64 x i16> zeroinitializer, <64 x i16>* %a0, align 128
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store <32 x i32> %t3, <32 x i32>* %a1, align 128
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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