121 lines
3.8 KiB
LLVM
121 lines
3.8 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-LABEL: test0000:
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; CHECK: v0.h = vasl(v0.h,r0)
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define <64 x i16> @test0000(<64 x i16> %a0, i16 %a1) #0 {
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%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
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%v0 = shl <64 x i16> %a0, %b1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0001:
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; CHECK: v0.h = vasr(v0.h,r0)
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define <64 x i16> @test0001(<64 x i16> %a0, i16 %a1) #0 {
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%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
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%v0 = ashr <64 x i16> %a0, %b1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0002:
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; CHECK: v0.uh = vlsr(v0.uh,r0)
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define <64 x i16> @test0002(<64 x i16> %a0, i16 %a1) #0 {
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%b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
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%b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
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%v0 = lshr <64 x i16> %a0, %b1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0010:
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; CHECK: v0.w = vasl(v0.w,r0)
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define <32 x i32> @test0010(<32 x i32> %a0, i32 %a1) #0 {
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%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
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%v0 = shl <32 x i32> %a0, %b1
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: test0011:
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; CHECK: v0.w = vasr(v0.w,r0)
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define <32 x i32> @test0011(<32 x i32> %a0, i32 %a1) #0 {
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%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
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%v0 = ashr <32 x i32> %a0, %b1
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: test0012:
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; CHECK: v0.uw = vlsr(v0.uw,r0)
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define <32 x i32> @test0012(<32 x i32> %a0, i32 %a1) #0 {
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%b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
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%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
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%v0 = lshr <32 x i32> %a0, %b1
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: test0013:
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; CHECK: v0.w += vasl(v1.w,r0)
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define <32 x i32> @test0013(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
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%b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
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%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
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%v0 = shl <32 x i32> %a1, %b1
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%v1 = add <32 x i32> %a0, %v0
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ret <32 x i32> %v1
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}
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; CHECK-LABEL: test0014:
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; CHECK: v0.w += vasr(v1.w,r0)
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define <32 x i32> @test0014(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
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%b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
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%b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
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%v0 = ashr <32 x i32> %a1, %b1
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%v1 = add <32 x i32> %a0, %v0
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ret <32 x i32> %v1
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}
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; CHECK-LABEL: test0020:
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; CHECK: v0.h = vasl(v0.h,v1.h)
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define <64 x i16> @test0020(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%v0 = shl <64 x i16> %a0, %a1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0021:
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; CHECK: v0.h = vasr(v0.h,v1.h)
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define <64 x i16> @test0021(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%v0 = ashr <64 x i16> %a0, %a1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0022:
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; CHECK: v0.h = vlsr(v0.h,v1.h)
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define <64 x i16> @test0022(<64 x i16> %a0, <64 x i16> %a1) #0 {
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%v0 = lshr <64 x i16> %a0, %a1
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ret <64 x i16> %v0
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}
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; CHECK-LABEL: test0030:
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; CHECK: v0.w = vasl(v0.w,v1.w)
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define <32 x i32> @test0030(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%v0 = shl <32 x i32> %a0, %a1
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: test0031:
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; CHECK: v0.w = vasr(v0.w,v1.w)
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define <32 x i32> @test0031(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%v0 = ashr <32 x i32> %a0, %a1
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ret <32 x i32> %v0
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}
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; CHECK-LABEL: test0032:
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; CHECK: v0.w = vlsr(v0.w,v1.w)
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define <32 x i32> @test0032(<32 x i32> %a0, <32 x i32> %a1) #0 {
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%v0 = lshr <32 x i32> %a0, %a1
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ret <32 x i32> %v0
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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