144 lines
3.5 KiB
LLVM
144 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv7em %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv6 %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s
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; RUN: llc -mtriple=armv8 %s -o - | FileCheck %s
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; CHECK-LABEL: sxtb16_ror_8
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; CHECK: sxtb16 r0, r0, ror #8
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define i32 @sxtb16_ror_8(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 8
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%shl.i = shl i32 %a, 24
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: sxtb16_ror_16
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; CHECK: sxtb16 r0, r0, ror #16
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define i32 @sxtb16_ror_16(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 16
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%shl.i = shl i32 %a, 16
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: sxtb16_ror_24
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; CHECK: sxtb16 r0, r0, ror #24
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define i32 @sxtb16_ror_24(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 24
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%shl.i = shl i32 %a, 8
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtb16_ror_8
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; CHECK: uxtb16 r0, r0, ror #8
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define i32 @uxtb16_ror_8(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 8
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%shl.i = shl i32 %a, 24
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtb16_ror_16
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; CHECK: uxtb16 r0, r0, ror #16
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define i32 @uxtb16_ror_16(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 16
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%shl.i = shl i32 %a, 16
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtb16_ror_24
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; CHECK: uxtb16 r0, r0, ror #24
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define i32 @uxtb16_ror_24(i32 %a) {
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entry:
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%shr.i = lshr i32 %a, 24
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%shl.i = shl i32 %a, 8
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtb16(i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: sxtab16_ror_8
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; CHECK: sxtab16 r0, r0, r1, ror #8
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define i32 @sxtab16_ror_8(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 8
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%shl.i = shl i32 %b, 24
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: sxtab16_ror_16
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; CHECK: sxtab16 r0, r0, r1, ror #16
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define i32 @sxtab16_ror_16(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 16
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%shl.i = shl i32 %b, 16
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: sxtab16_ror_24
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; CHECK: sxtab16 r0, r0, r1, ror #24
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define i32 @sxtab16_ror_24(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 24
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%shl.i = shl i32 %b, 8
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.sxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtab16_ror_8
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; CHECK: uxtab16 r0, r0, r1, ror #8
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define i32 @uxtab16_ror_8(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 8
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%shl.i = shl i32 %b, 24
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtab16_ror_16
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; CHECK: uxtab16 r0, r0, r1, ror #16
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define i32 @uxtab16_ror_16(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 16
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%shl.i = shl i32 %b, 16
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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; CHECK-LABEL: uxtab16_ror_24
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; CHECK: uxtab16 r0, r0, r1, ror #24
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define i32 @uxtab16_ror_24(i32 %a, i32 %b) {
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entry:
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%shr.i = lshr i32 %b, 24
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%shl.i = shl i32 %b, 8
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%or.i = or i32 %shl.i, %shr.i
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%0 = tail call i32 @llvm.arm.uxtab16(i32 %a, i32 %or.i)
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ret i32 %0
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}
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declare i32 @llvm.arm.sxtb16(i32)
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declare i32 @llvm.arm.uxtb16(i32)
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declare i32 @llvm.arm.sxtab16(i32, i32)
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declare i32 @llvm.arm.uxtab16(i32, i32)
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