173 lines
4.8 KiB
YAML
173 lines
4.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
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---
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name: shl_cimm_32
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: shl_cimm_32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 24, 23
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; CHECK: $w0 = COPY [[UBFMWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = G_CONSTANT i32 8
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%2:gpr(s32) = G_SHL %0, %1(s32)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_cimm_64
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: shl_cimm_64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 56, 55
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 8
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%2:gpr(s64) = G_SHL %0, %1(s64)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: lshr_cimm_32
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: lshr_cimm_32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 8, 31
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; CHECK: $w0 = COPY [[UBFMWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%3:gpr(s64) = G_CONSTANT i64 8
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%2:gpr(s32) = G_LSHR %0, %3(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: lshr_cimm_64
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: lshr_cimm_64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[COPY]], 8, 63
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 8
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%2:gpr(s64) = G_LSHR %0, %1(s64)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: ashr_cimm_32
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: ashr_cimm_32
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 8, 31
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; CHECK: $w0 = COPY [[SBFMWri]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%3:gpr(s64) = G_CONSTANT i64 8
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%2:gpr(s32) = G_ASHR %0, %3(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ashr_cimm_64
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x0
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; CHECK-LABEL: name: ashr_cimm_64
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[COPY]], 8, 63
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; CHECK: $x0 = COPY [[SBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s64) = COPY $x0
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%1:gpr(s64) = G_CONSTANT i64 8
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%2:gpr(s64) = G_ASHR %0, %1(s64)
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$x0 = COPY %2(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: lshr_32_notimm64
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: lshr_32_notimm64
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
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; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]]
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; CHECK: $w0 = COPY [[LSRVWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%3:gpr(s64) = G_CONSTANT i64 8
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%4:gpr(s64) = G_AND %3, %3
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%2:gpr(s32) = G_LSHR %0, %4(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ashr_32_notimm64
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: ashr_32_notimm64
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 8
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32
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; CHECK: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[SUBREG_TO_REG]], 8000
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ANDXri]].sub_32
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; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]]
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; CHECK: $w0 = COPY [[ASRVWr]]
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; CHECK: RET_ReallyLR implicit $w0
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%0:gpr(s32) = COPY $w0
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%3:gpr(s64) = G_CONSTANT i64 8
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%4:gpr(s64) = G_AND %3, %3
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%2:gpr(s32) = G_ASHR %0, %4(s64)
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$w0 = COPY %2(s32)
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RET_ReallyLR implicit $w0
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...
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