201 lines
5.2 KiB
YAML
201 lines
5.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s
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name: test_v8s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v8s8
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[CLZv8i8_:%[0-9]+]]:fpr64 = CLZv8i8 [[COPY]]
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; CHECK: $d0 = COPY [[CLZv8i8_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<8 x s8>) = COPY $d0
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%1:fpr(<8 x s8>) = G_CTLZ %0(<8 x s8>)
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$d0 = COPY %1(<8 x s8>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v4s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v4s16
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[CLZv4i16_:%[0-9]+]]:fpr64 = CLZv4i16 [[COPY]]
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; CHECK: $d0 = COPY [[CLZv4i16_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<4 x s16>) = COPY $d0
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%1:fpr(<4 x s16>) = G_CTLZ %0(<4 x s16>)
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$d0 = COPY %1(<4 x s16>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v2s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_v2s32
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[CLZv2i32_:%[0-9]+]]:fpr64 = CLZv2i32 [[COPY]]
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; CHECK: $d0 = COPY [[CLZv2i32_]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s32>) = COPY $d0
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%1:fpr(<2 x s32>) = G_CTLZ %0(<2 x s32>)
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$d0 = COPY %1(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: test_s64
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; CHECK: liveins: $d0
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
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; CHECK: [[CLZXr:%[0-9]+]]:gpr64 = CLZXr [[COPY1]]
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; CHECK: $d0 = COPY [[CLZXr]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s64) = COPY $d0
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%2:gpr(s64) = COPY %0(s64)
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%1:gpr(s64) = G_CTLZ %2(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: test_s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $s0
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; CHECK-LABEL: name: test_s32
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; CHECK: liveins: $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
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; CHECK: [[CLZWr:%[0-9]+]]:gpr32 = CLZWr [[COPY1]]
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; CHECK: $s0 = COPY [[CLZWr]]
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; CHECK: RET_ReallyLR implicit $s0
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%0:fpr(s32) = COPY $s0
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%2:gpr(s32) = COPY %0(s32)
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%1:gpr(s32) = G_CTLZ %2(s32)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: test_v16s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v16s8
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CLZv16i8_:%[0-9]+]]:fpr128 = CLZv16i8 [[COPY]]
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; CHECK: $q0 = COPY [[CLZv16i8_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<16 x s8>) = COPY $q0
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%1:fpr(<16 x s8>) = G_CTLZ %0(<16 x s8>)
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$q0 = COPY %1(<16 x s8>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v8s16
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v8s16
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CLZv8i16_:%[0-9]+]]:fpr128 = CLZv8i16 [[COPY]]
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; CHECK: $q0 = COPY [[CLZv8i16_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:fpr(<8 x s16>) = G_CTLZ %0(<8 x s16>)
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$q0 = COPY %1(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v4s32
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v4s32
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[CLZv4i32_:%[0-9]+]]:fpr128 = CLZv4i32 [[COPY]]
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; CHECK: $q0 = COPY [[CLZv4i32_]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = G_CTLZ %0(<4 x s32>)
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$q0 = COPY %1(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: test_v2s64
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: test_v2s64
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; CHECK: liveins: $q0
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; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
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; CHECK: [[CTLZ:%[0-9]+]]:fpr(<2 x s64>) = G_CTLZ [[COPY]](<2 x s64>)
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; CHECK: $q0 = COPY [[CTLZ]](<2 x s64>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(<2 x s64>) = COPY $q0
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%1:fpr(<2 x s64>) = G_CTLZ %0(<2 x s64>)
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$q0 = COPY %1(<2 x s64>)
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RET_ReallyLR implicit $q0
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